公开(公告)号：EP2400499B1

公开(公告)日：2018-12-05

申请号：EP11154227.0

申请日：2011-02-11

申请人： Samsung Electronics Co., Ltd.

发明人： Kim, Young-bae ,  Lee, Chang-bum ,  Lee, Dong-soo ,  Kim, Chang-jung ,  Lee, Myoung-jae ,  Chang, Man ,  Lee, Seung-ryul

IPC分类号： G11C13/00

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32

摘要： Methods of operating semiconductor devices that include variable resistance devices include writing first data to a semiconductor device by applying a reset pulse voltage to the variable resistance device so that the variable resistance device is switched from a first resistance state to a second resistance state, and writing second data to the semiconductor device by applying a set pulse voltage to the variable resistance device so that the variable resistance device is switched from the second resistance state to the first resistance state. The reset pulse voltage is higher than the set pulse voltage, and a resistance in the second resistance state is greater than in the first resistance state

公开(公告)号：EP3324412A1

公开(公告)日：2018-05-23

申请号：EP17197333.2

申请日：2017-10-19

申请人： NXP USA, Inc.

发明人： ROY, Anirban ,  SADD, Michael A.

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C7/062 ,  G11C11/1673 ,  G11C11/4091 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2013/005 ,  G11C2013/0057 ,  G11C2207/068 ,  G11C2213/15 ,  G11C2213/79

摘要： A memory device includes a sense amplifier coupled to a first read voltage during a first phase of a read operation and a second read voltage during a second phase of the read operation. A first and second bias voltages are based on the first and second read voltages and corresponding current on a bit line. A first capacitor includes a terminal coupled to the first and second bias voltages. A first amplifier includes an input coupled to another terminal of the first capacitor and another input coupled to a common mode voltage during the first phase and to a reference voltage during the second phase. A second capacitor includes a terminal coupled to an output of the first amplifier. A second amplifier includes an inverting input coupled to another terminal of the second capacitor and another input coupled to a common mode voltage.

公开(公告)号：EP2618393B1

公开(公告)日：2018-04-18

申请号：EP13151331.9

申请日：2013-01-15

申请人： Xerox Corporation

发明人： McCreery, Richard L. ,  Shoute, Lian C T ,  Wu, Yiliang

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： G11C13/0016 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/17 ,  G11C2213/53 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/14

摘要： A non-volatile memory device including at least a first electrode and a second electrode provided on a substrate, the first and second electrodes being separated from each other; an organic semiconductive polymer electrically connecting the first and second electrodes; an electrolyte in contact with the organic semiconductive polymer; and a third electrode that is not in contact with the first electrode, the second electrode, and the organic semiconductive polymer; wherein the organic semiconductive polymer has a first redox state in which it exhibits a first conductivity, and a second redox state in which it exhibits a second conductivity.

公开(公告)号：EP2557106B1

公开(公告)日：2017-05-17

申请号：EP11766086.0

申请日：2011-03-31

申请人： Postech Academy-Industry Foundation

发明人： REE, Moonhor ,  PARK, Samdae ,  HAM, Suk Gyu ,  KIM, Jin Chul ,  KO, Yong-gi ,  CHOI, Jun Man ,  LEE, Taek Joon ,  KIM, Dong Min ,  KIM, Kyungtae ,  KWON, Wonsang

IPC分类号： C08G73/10 ,  C08L79/08 ,  H01L27/115 ,  G11C13/00 ,  G11C13/04 ,  H01L51/05 ,  H01L51/00

CPC分类号： H01L51/0035 ,  C08G73/101 ,  G11C13/0016 ,  G11C13/04 ,  G11C2213/15 ,  G11C2213/72 ,  H01L51/0002 ,  H01L51/0591 ,  H01L51/0595

公开(公告)号：EP2907135B1

公开(公告)日：2016-08-31

申请号：EP13783431.3

申请日：2013-10-08

申请人： Saudi Basic Industries Corporation

发明人： ALSHAREEF, Husam N. ,  KHAN, Mohd Adnan ,  BHANSALI, Unnat S. ,  ALMADHOUN, Mahmoud

IPC分类号： G11C11/34 ,  H01L27/28 ,  H01L51/30

CPC分类号： H01L45/1253 ,  G11C13/0016 ,  G11C2213/15 ,  H01L27/281 ,  H01L45/16 ,  H01L51/0037 ,  H01L51/0575 ,  H01L51/0591 ,  H01L51/102

公开(公告)号：EP2689423A1

公开(公告)日：2014-01-29

申请号：EP11861820.6

申请日：2011-09-16

申请人： Kabushiki Kaisha Toshiba, Inc.

发明人： ICHIHARA, Reika ,  MATSUSHITA, Daisuke ,  FUJII, Shosuke

IPC分类号： G11C13/00 ,  H01L27/105 ,  H01L45/00 ,  H01L49/00

CPC分类号： G11C13/0069 ,  G11C11/5614 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/005 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/33 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/148

摘要： According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

摘要翻译： 根据一个实施例，电阻变化存储器包括存储单元和控制电路。 存储单元包括第一和第二电极以及设置在第一电极和第二电极之间的可变电阻层。 控制电路在第一电极和第二电极之间施加电压以进行写入，擦除和读取。 在写入期间，控制电路在第一电极和第二电极之间施加第一电压脉冲，然后在施加第一电压脉冲之后施加与第一电压脉冲不同极性的第二电压脉冲。

公开(公告)号：EP2622664A1

公开(公告)日：2013-08-07

申请号：EP10857972.3

申请日：2010-09-27

申请人： Hewlett-Packard Development Company, L.P.

发明人： YANG, Jianhua ,  ZHANG, Minxian, Max ,  WILLIAMS, R., Stanley

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L45/14 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/52 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/149 ,  H01L45/1608

摘要： A memristor includes a first electrode formed of a first metal, a second electrode formed of a second material, wherein the second material comprises a different material from the first metal, and a switching layer positioned between the first electrode and the second electrode. The switching layer is formed of a composition of a first material comprising the first metal and a second nonmetal material, in which the switching layer is in direct contact with the first electrode and in which at least one conduction channel is configured to be formed in the switching layer from an interaction between the first metal and the second nonmetal material.

摘要翻译： 忆阻器包括由第一金属形成的第一电极，由第二材料形成的第二电极，其中第二材料包括与第一金属不同的材料，以及位于第一电极和第二电极之间的开关层。 切换层由包含第一金属和第二非金属材料的第一材料的组合物形成，其中切换层与第一电极直接接触，并且其中至少一个导电沟道被配置为在 从第一金属和第二非金属材料之间的相互作用切换层。

公开(公告)号：EP2436011A2

公开(公告)日：2012-04-04

申请号：EP10724255.4

申请日：2010-05-08

申请人： Forschungszentrum Jülich Gmbh ,  Rheinisch-Westfälische Technische Hochschule Aachen (RWTH)

发明人： LINN, Eike ,  KÜGELER, Carsten ,  ROSEZIN, Roland Daniel ,  WASER, Rainer

IPC分类号： G11C13/00 ,  G11C13/02 ,  G11C11/56 ,  H03K19/177

CPC分类号： G11C13/0002 ,  G11C13/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H03K19/177

摘要： Disclosed is a memory element, a stack, and to a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.

摘要翻译： 公开了一种存储元件，堆叠和存储器矩阵，其中可以使用存储元件。 还公开了一种用于操作存储器矩阵的方法，以及用于确定包括存储器元件的阵列中的逻辑运算的真实值的方法。 存储元件具有至少第一稳定状态0和第二稳定状态1.通过施加第一写入电压V0，该存储元件可以被转移到高阻抗状态0并且通过施加第二写入电压V1，它可以 被转移到同样的高阻抗状态1.通过施加读取电压VR，其量值小于写入电压V0和V1，存储元件表现出不同的电阻值。 在存储矩阵中发生的寄生电流路径中，存储元件充当高阻抗电阻，原则上不限于单极开关。 已经公开了一种使用包括可以变成用于任意逻辑运算的门的存储器元件的阵列的方法。

公开(公告)号：EP1501124B1

公开(公告)日：2011-06-08

申请号：EP03719228.3

申请日：2003-04-25

申请人： Japan Science and Technology Agency

发明人： SAKAMOTO, Toshitsugu ,  AONO, Masakazu ,  HASEGAWA, Tsuyoshi ,  NAKAYAMA, Tomonobu ,  SUNAMURA, Hiroshi ,  KAWAURA, Hisao ,  SUGIBAYASHI, Naohiko

IPC分类号： H01L45/00 ,  H03K19/173 ,  G11C13/02

CPC分类号： G11C13/0011 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/101 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/144 ,  H01L45/1633 ,  H01L2924/0002 ,  H01L2924/00

摘要： A solid electrolyte switching device (10, 10’, 20, 20’) comprises a first interconnection layer (13) provided on a substrate (11) covered with an insulating layer, an ion supply layer (17) provided on the first interconnection layer (13), a solid electrolyte layer (16) provided on the ion supply layer (17), an interlayer insulating layer (12) covering the first interconnection layer (13), the ion supply layer (17), and the solid electrolyte layer (16) and having a via hole, a counter electrode layer (15) so disposed as to be in contact with the solid electrolyte layer(16) through the via hole, and a second interconnection layer(14) covering the counter electrode layer(15). The on/off state can be arbitrarily set by a threshold voltage applied between the ion supply layer (17) and the counter electrode layer (15). Thus a nonvolatile, low on-resistance switching device is provided.

公开(公告)号：EP2221828A1

公开(公告)日：2010-08-25

申请号：EP10004664.8

申请日：2005-01-28

申请人： Zettacore, Inc.

发明人： Kuhr, Werner G. ,  Gallo, Antonio R.

IPC分类号： G11C13/02 ,  H01L51/00

CPC分类号： G11C13/0069 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0009 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0033 ,  G11C13/004 ,  G11C16/3431 ,  G11C2013/0047 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/285 ,  H01L51/0077 ,  H01L51/0595

摘要： A molecular memory element comprising a switching device; at least a first bit line and a first word line coupled to said switching device; and an array of storage locations, each coupled to a bit line and a word line, said elements comprising a first electrode with storage molecules comprising redox active molecules, and said array comprising a second electrode.

摘要翻译： 一种分子存储元件，包括开关器件; 至少第一位线和耦合到所述开关器件的第一字线; 以及存储位置阵列，每个存储位置都耦合到位线和字线，所述元件包括具有包含氧化还原活性分子的存储分子的第一电极，所述阵列包括第二电极。