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    ARRAYS OF MEMORY CELLS AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS
    3.
    发明授权
    ARRAYS OF MEMORY CELLS AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS 有权

    公开(公告)号：EP2954556B1

    公开(公告)日：2018-07-11

    申请号：EP14749460.3

    申请日：2014-01-13

    Applicant: Micron Technology, Inc.

    Inventor： LIU, Jun ,  PAREKH, Kunal, R.

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

    RESISTIVE MEMORY AND METHOD OF FABRICATING THE SAME
    4.
    发明公开
    RESISTIVE MEMORY AND METHOD OF FABRICATING THE SAME 审中-公开
    RESISTIVER SPEICHER UND VERFAHREN ZUR HERSTELLUNG DAVON

    公开(公告)号：EP3163642A1

    公开(公告)日：2017-05-03

    申请号：EP16162207

    申请日：2016-03-24

    Applicant: WINBOND ELECTRONICS CORP

    Inventor： HSU PO-YEN ,  SHEN TING-YING ,  HO CHIA-HUA ,  FU CHIH-CHENG ,  CHEN FREDERICK

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

    Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.

    Abstract translation: 提供了电阻式存储器和制造该电阻式存储器的方法。 电阻式存储器包括第一电极，第二电极，可变电阻层，氧气交换层和保护层。 第一电极和第二电极彼此相对地布置。 可变电阻层布置在第一电极和第二电极之间。 氧气交换层布置在可变电阻层和第二电极之间。 保护层至少设置在氧气交换层的侧壁上。

    RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION
    8.
    发明公开
    RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION 审中-公开
    RESISTIVER SPEICHER MIT VERFEINERTER FILAMENTBILDUNG

    公开(公告)号：EP2847790A4

    公开(公告)日：2016-01-13

    申请号：EP13787159

    申请日：2013-05-07

    Applicant: MICRON TECHNOLOGY INC

    Inventor： MARSH EUGENE P ,  LIU JUN

    IPC: H01L45/00

    CPC classification number: H01L45/085 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

    Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.

    Abstract translation: 这里描述了具有受限制的细丝形成的电阻记忆。 一个或多个方法实施方案包括在硅材料上形成具有硅材料和氧化物材料的堆叠中的开口，以及在邻近硅材料的开口中形成氧化物材料，其中形成在开口中的氧化物材料限制在 电阻式存储单元到形成在开口中的由氧化物材料包围的区域。

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