公开(公告)号：EP0367707B1

公开(公告)日：1995-02-01

申请号：EP89480153.9

申请日：1989-09-26

申请人： International Business Machines Corporation

发明人： Bukowski, Eugene Raymond, Jr.

IPC分类号： H03F3/45

CPC分类号： H03F3/45968 ,  H03F2203/45214 ,  H03F2203/45342

公开(公告)号：EP0499645A4

公开(公告)日：1993-03-03

申请号：EP91915986

申请日：1991-09-12

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： YAMASHITA, MASAHIRO ,  NISHIMURA, HIROKAZU

IPC分类号： H03F1/32 ,  H03F3/45

CPC分类号： H03F3/45076 ,  H03F2203/45214

摘要： An operational amplifying circuit, the linearity of whose output voltage to the input voltage thereof can be ensured ranging from a first power supply to a second one. A differential circuit (1) comprising a first and a second FET transistor (T11, T12) having channels of a first conductive type, a current Miller circuit part (2) comprising a first and a second FET transistor (T13, T14) having channels of a second conductive type which are connected with the differential amplifying circuit (1) respectively, a constant current circuit part (3) which is connected to the differential amplifying circuit (1) on the second power supply (GND) side, and an output circuit part (4) comprising a third FET transistor (T7) of the second conductive type whose gate terminal is connected with the drain terminal of the second FET transistor (T12) and a constant current circuit. The potential (a) of the connecting part between the differential amplifying circuit part and the constant current circuit part (3) is set to zero volt or more when an input signal Vin is zero volt, and the potential difference between the potential (a) and the potential (b) of the gate of the third FET transistor is ensured in the whole range of the voltage change of the input signal Vin.

公开(公告)号：EP0157799B1

公开(公告)日：1988-03-02

申请号：EP84903393.1

申请日：1984-09-04

申请人： AT&T Corp.

发明人： BANU, Mihai

IPC分类号： H03F3/45 ,  G06G7/14

CPC分类号： H03F3/45183 ,  G06G7/14 ,  H03F3/45659 ,  H03F2203/45214 ,  H03F2203/45401 ,  H03F2203/45648 ,  H03F2203/45711

摘要： A common mode detector (10) for producing an output voltage (VA + VB)/2 in response to input voltages VA and VB contains a pair of MOS transitors (MA and MB) connected in series between a pair of input terminals A and B to which the input voltages (VA and VB) are to be applied. A separate feedback path runs from each input terminal (A, B) through a separate load device (LA2, LB2) to a gate control terminal of the respective MOS transistor (MA, MB) and a separate other feedback path runs from each input terminal (A, B) through a separate other load device (LA3, LB3) to a substrate terminal (SA, SB) of the respective MOS transistors. In this way, the respective feedback paths deliver to the respective gate terminals respective voltages equal to (VDD + VA)/2 and (VDD + VB)/2, respectively, while the other feedback paths deliver to the substrates of the respective MOS transistors (MA, MB) respective substrate bias voltages equal to (VSS + VA)/2 and (VSS + VB)/2, whereby the common mode voltage (VA + VB)/2 is developed at a node (AB) between the pair of MOS transistors (MA, MB).

公开(公告)号：EP0499645A1

公开(公告)日：1992-08-26

申请号：EP91915986.3

申请日：1991-09-12

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： YAMASHITA, Masahiro ,  NISHIMURA, Hirokazu

IPC分类号： H03F3/45

CPC分类号： H03F3/45076 ,  H03F2203/45214

摘要： An operational amplifying circuit, the linearity of whose output voltage to the input voltage thereof can be ensured ranging from a first power supply to a second one. A differential circuit (1) comprising a first and a second FET transistor (T11, T12) having channels of a first conductive type, a current Miller circuit part (2) comprising a first and a second FET transistor (T13, T14) having channels of a second conductive type which are connected with the differential amplifying circuit (1) respectively, a constant current circuit part (3) which is connected to the differential amplifying circuit (1) on the second power supply (GND) side, and an output circuit part (4) comprising a third FET transistor (T7) of the second conductive type whose gate terminal is connected with the drain terminal of the second FET transistor (T12) and a constant current circuit. The potential (a) of the connecting part between the differential amplifying circuit part and the constant current circuit part (3) is set to zero volt or more when an input signal Vin is zero volt, and the potential difference between the potential (a) and the potential (b) of the gate of the third FET transistor is ensured in the whole range of the voltage change of the input signal Vin.

摘要翻译： 一种运算放大电路，其输出电压的输出电压的线性度可从第一电源到第二电源的范围确保。 一种包括具有第一导电类型的沟道的第一和第二FET晶体管（T11，T12）的差分电路（1），包括第一和第二FET晶体管（T13，T14）的电流密勒电路部分（2），具有通道 分别与差分放大电路（1）连接的第二导电类型的连接到第二电源（GND）侧的差动放大电路（1）的恒流电路部（3）和输出 电路部分（4）包括栅极端子与第二FET晶体管（T12）的漏极端子连接的第二导电类型的第三FET晶体管（T7）和恒流电路。 当输入信号Vin为零伏特时，差分放大电路部分和恒流电路部分（3）之间的连接部分的电势（a）被设置为零伏或更大，并且电位（a） 并且在输入信号Vin的电压变化的整个范围内确保第三FET晶体管的栅极的电位（b）。

公开(公告)号：EP0367707A3

公开(公告)日：1991-03-20

申请号：EP89480153.9

申请日：1989-09-26

申请人： International Business Machines Corporation

发明人： Bukowski, Eugene Raymond, Jr.

IPC分类号： H03F3/45

CPC分类号： H03F3/45968 ,  H03F2203/45214 ,  H03F2203/45342

摘要： The circuit arrangement for adjusting offset voltages associated with operational amplifiers, includes an operational amplifier (18) whose input stage includes a current source (Is) coupled to a differential pair of input devices (14, 16). The physical characteristics of the devices (14, 16) are such that an intentional offset voltage greater than the normal op amp offset voltage is provided in the input stage. The output terminal of the operational amplifier (18) is connected to the substrate terminal of one (14) of the input devices. The offset voltages of other op amps can be negated by interconnect­ing the substrate terminal of one device in each input differential pair to the output terminal of the generator op amp and creating an intentional offset voltage in the input differential pair of each op amp.

公开(公告)号：EP0367707A2

公开(公告)日：1990-05-09

申请号：EP89480153.9

申请日：1989-09-26

申请人： International Business Machines Corporation

发明人： Bukowski, Eugene Raymond, Jr.

IPC分类号： H03F3/45

CPC分类号： H03F3/45968 ,  H03F2203/45214 ,  H03F2203/45342

摘要： The circuit arrangement for adjusting offset voltages associated with operational amplifiers, includes an operational amplifier (18) whose input stage includes a current source (Is) coupled to a differential pair of input devices (14, 16). The physical characteristics of the devices (14, 16) are such that an intentional offset voltage greater than the normal op amp offset voltage is provided in the input stage. The output terminal of the operational amplifier (18) is connected to the substrate terminal of one (14) of the input devices. The offset voltages of other op amps can be negated by interconnect­ing the substrate terminal of one device in each input differential pair to the output terminal of the generator op amp and creating an intentional offset voltage in the input differential pair of each op amp.

摘要翻译： 用于调整与运算放大器相关的偏移电压的电路装置包括运算放大器（18），其输入级包括耦合到差分输入装置（14,16）的电流源（Is）。 器件（14,16）的物理特性使得在输入级中提供大于正常运放偏移电压的有意偏移电压。 运算放大器（18）的输出端子连接到一个（14）输入装置的基板端子。 通过将每个输入差分对中的一个器件的衬底端子与发生器运算放大器的输出端相互连接，并在每个运算放大器的输入差分对中产生有意的偏移电压，可以消除其他运算放大器的偏移电压。

公开(公告)号：EP0157799A1

公开(公告)日：1985-10-16

申请号：EP84903393.0

申请日：1984-09-04

申请人： AT&T Corp.

发明人： BANU, Mihai

IPC分类号： G01R19 ,  G06G7 ,  H03F3

CPC分类号： H03F3/45183 ,  G06G7/14 ,  H03F3/45659 ,  H03F2203/45214 ,  H03F2203/45401 ,  H03F2203/45648 ,  H03F2203/45711

摘要： Un détecteur de mode commun (10) servant à produire une tension de sortie (VA + VB)/2 en réponse aux tensions d'entrée VA et VB contient une paire de transistors MOS (MA et MB) reliés en série entre une paire de terminaux d'entrée A et B auxquels doivent être appliquées les tensions d'entrée (VA et VB). Un chemin séparé de réaction va de chaque terminal d'entrée (A, B) par l'intermédiaire d'un dispositif de charge séparé (LA2, LB2) jusqu'à un terminal de commande de porte du transistor MOS respectif (MA, MB) et un autre chemin séparé de réaction va de chaque terminal d'entrée (A, B) au travers d'un autre dispositif de charge séparé (LA3, LB3) vers un terminal de substrat (SA, SB) des transistors MOS respectifs. De la sorte, les chemins de réaction respectifs délivrent aux terminaux de porte respectifs des signaux respectifs égaux à (VDD + VA)/2 et (VDD + VB)/2, respectivement, tandis que les autres chemins de réaction délivrent aux substrats des transistors MOS respectifs (MA, MB) des tensions respectives de polarisation de substrat égales à (VSS + VA)/2 et (VSS + VB)/2, la tension de mode commun (VA + VB)/2 étant développée en un point nodal (AB) situé entre la paire de transistors MOS (MA, MB).