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23 条记录 (耗时 0.011 秒)

    CIRCUIT FOR CALIBRATION MEASUREMENTS, METHOD, COMPUTER PROGRAM, AND ELECTRONIC DEVICE
    1.
    发明公开
    CIRCUIT FOR CALIBRATION MEASUREMENTS, METHOD, COMPUTER PROGRAM, AND ELECTRONIC DEVICE 审中-公开
    电路校准测量方法，计算机程序和电子设备

    公开(公告)号：EP3075074A1

    公开(公告)日：2016-10-05

    申请号：EP13805296.4

    申请日：2013-11-27

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： EK, Staffan ,  MU, Fenghao ,  ANDERSSON, Martin

    IPC分类号： H03H7/01

    CPC分类号： H03H7/0153 ,  G01R35/005 ,  H03H2210/043 ,  H03K5/24

    摘要： A circuit for calibration measurements comprises a first and a second current sources (202, 203, 502) arranged to provide current outputs; a resistor (204, 504) connected between the first current source (202, 502) and a reference voltage; a capacitor (205, 505) connected between the second current source (203, 502) and the reference voltage; a discharge switch (207, 507) connected in parallel with the capacitor (205, 505) and arranged to selectively discharge the capacitor (205, 505); a comparator circuit (206, 506) arranged to compare voltages across the resistor (204, 504) and the capacitor (205, 505) and output a signal when voltage across the capacitor reaches the voltage across the resistor; and a controller (208, 608) having a clock signal input (CLK) and connected to the output of the comparator circuit (206, 506). The controller (208, 608) is arranged to control the discharge switch (207, 507) to discharge the capacitor (205, 505), change state of the switch (207, 507) to enable charging of the capacitor (205, 505) and count clock signal pulses until the comparator provides the signal when voltage across the capacitor reaches the voltage across the resistor, wherein the controller (208, 608) is arranged to determine a calibration measurement from counted number of clock signal pulses. A method, computer program and electronic device are also disclosed.

    CALIBRATING A LOOP-FILTER OF A PHASE LOCKED LOOP
    3.
    发明公开
    CALIBRATING A LOOP-FILTER OF A PHASE LOCKED LOOP 审中-公开
    循环的校准滤波器锁相环

    公开(公告)号：EP1658678A1

    公开(公告)日：2006-05-24

    申请号：EP04744244.7

    申请日：2004-08-12

    申请人： Nokia Corporation

    发明人： VILHONEN, Sami ,  MELAVA, Jari

    IPC分类号： H03L7/093 ,  H03H7/06 ,  H03H7/54

    CPC分类号： H03H7/54 ,  H03H7/0153 ,  H03H7/06 ,  H03H7/12 ,  H03H2210/043 ,  H03L7/0891 ,  H03L7/093

    摘要： The invention relates to a method of automatically calibrating a loop-filter of a phase locked loop, which loop-filter comprises at least one RC-filter component and is integrated on a single chip together with at least one RC-filter component of another entity than the phase locked loop. In order to simplify a calibration of the loop-filter, the method comprises tuning the at least one RC-filter component of the loop-filter based on measurements performed on the at least one RC-filter component of the other entity. The invention relates equally to an integrated circuit chip comprising means for realizing this method and to a unit including such a chip.

    High-precision calibration circuit calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
    5.
    发明公开
    High-precision calibration circuit calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance 有权
    用于校准集成电路的可调电容的时间常数依赖于电容高精度校准电路

    公开(公告)号：EP1962420A1

    公开(公告)日：2008-08-27

    申请号：EP07425099.4

    申请日：2007-02-23

    申请人： STMicroelectronics S.r.l.

    发明人： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Nicollini, Germano

    IPC分类号： H03H1/02 ,  H03H7/01

    CPC分类号： H03H7/0153 ,  H03H1/02 ,  H03H2210/021 ,  H03H2210/043

    摘要： A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitance ((C var (REG_BUS)) and including a calibration loop (U_CV, CMP, TG_SAR), suitable to carry out a calibration cycle (C_LOOP) in several sequential steps (St_1, ..., St4), comprising:
    - a controllable capacitance unit (U_CV) suitable to receive a control signal (SAR_BUS) at the beginning of a calibration step and including an array of switched capacitors (C_AR1) that can be selectively activated by the control signal to be connected to a first common node (N_u) having, at the end of an integration interval (P2), a voltage value (VRC) depending on the total capacitance value of the activated capacitors;
    - an assessment unit (CMP) suitable to compare this voltage value (VRC) with a reference voltage to output a logic signal (OUT_CMP) that, based on the comparison result can be subjected to a transition between first and second logic levels;
    - a control and timing unit (TG_SAR) suitable to receive the logic signal (OUT_CMP) and to change the control signal (SAR_BUS) based thereon, in order to carry out a subsequent calibration step,

    characterized in that
    in said calibration step is provided, at the end of said integration interval (P2) a comparison interval (P3) of a preset duration, which allows a transition (tl,t4) of the logic signal (OUT_CMP) to occur prior to the beginning of said consecutive calibration step.

    摘要翻译： 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容（C（VAR（REG_BUS））和包括校准环路（U_CV，CMP，TG_SAR），适合在几个连续的步骤来进行校准周期（C_LOOP）（ST_1，...，圣4 ），包括： - 一个可控电容单元（U_CV）适合于在校准步骤的开始接收的控制信号（SAR_BUS），并在开关电容器阵列（C_AR1）包括也可以由控制信号被选择性地激活以连接 到第一公共节点（N_u），其具有，在一个积分区间（P2）结束时，一个电压值（VRC）根据激活的电容器的总电容值; - 评估单元（CMP）适合于比较该电压 值（VRC）与参考 ENCE电压以输出逻辑信号（OUT_CMP），基于该比较结果可以进行第一和第二逻辑电平之间的转变; - 控制和定时单元（TG_SAR）适合于接收所述逻辑信号（OUT_CMP）和改变控制信号（SAR_BUS）基于其，以便进行随后的校准步骤中，在“那个”中设置的所述校准步骤为特征的， 在逻辑信号（OUT_CMP）的所述积分间隔（P2）在预设持续时间的比较区间（P3），它允许一个过渡（TL，T4）的端部之前，所述连续校准步骤的开始时发生。

    On-chip R-C time constant calibration
    6.
    发明公开
    On-chip R-C time constant calibration 审中-公开
    片上Kalibrierung der Zeitkonstante R-C

    公开(公告)号：EP1786101A2

    公开(公告)日：2007-05-16

    申请号：EP06023361.6

    申请日：2006-11-09

    申请人： Quantek, Inc.

    发明人： Lau, Wai ,  Tseng, Chao-Wen ,  Chiu, Wei-Chien ,  Chen, Ying-Chi

    IPC分类号： H03H11/12 ,  H03B27/00 ,  H03K3/0231

    CPC分类号： H03H11/1291 ,  H03H7/0153 ,  H03H2210/043 ,  H03K3/0231 ,  H03K3/02337

    摘要： An integrated tuner (100) includes circuitry (105) to receive a television signal, a quadrature mixer (110) coupled to the output of the circuitry, a polyphase filter (120) coupled to the output of the quadrature mixer (110), a relaxation oscillator (140), and a digital calibration module (130). The relaxation oscillator (140) generates a clock having a period that is directly proportional to the on-chip RC time constant. The clock is fed into a counter (160) of the digital calibration module (130). The counter (160) is started and stopped at predefined time intervals by a finite state machine (170). The finite state machine (170) updates the calibration code based on a successive approximation algorithm according to the end count results received from the counter (160). The digital calibration module (130) outputs the updated calibration code to the polyphase filter (120) and to the relaxation oscillator (140).

    摘要翻译： 集成调谐器（100）包括接收电视信号的电路（105），耦合到电路的输出的正交混频器（110），耦合到正交混频器（110）的输出的多相滤波器（120） 张弛振荡器（140）和数字校准模块（130）。 张弛振荡器（140）产生具有与片上RC时间常数成正比的周期的时钟。 时钟被馈送到数字校准模块（130）的计数器（160）。 通过有限状态机（170）以预定的时间间隔启动和停止计数器（160）。 有限状态机（170）根据从计数器（160）接收的结束计数结果，基于逐次逼近算法更新校准码。 数字校准模块（130）将更新的校准代码输出到多相滤波器（120）和张弛振荡器（140）。

    Tuning circuit
    7.
    发明公开
    Tuning circuit 审中-公开
    调谐电路

    公开(公告)号：EP1737127A1

    公开(公告)日：2006-12-27

    申请号：EP06012881.6

    申请日：2006-06-22

    申请人： Integrant Technologies Inc.

    发明人： Minsu, Jeong ,  Seyeob, Kim

    IPC分类号： H03H11/12

    CPC分类号： H03H11/1291 ,  H03H7/0153 ,  H03H2210/021 ,  H03H2210/043

    摘要： The present invention relates to a filter and, more particularly, to a tuning circuit of a filter for correcting a cut-off frequency of the filter. The tuning circuit comprises a current generation unit (210) having a first transistor (MN21) and a variable resistor unit (213), and a capacitance correction unit (220) having a second transistor (MN22), a capacitor unit (223), an up-down counter (222) and a selection unit (S4) for selecting a control path of the up-down counter for varying the resistance or capacitance.

    摘要翻译： 滤波器的调谐电路本发明涉及一种滤波器，更具体地说，涉及一种用于校正滤波器的截止频率的滤波器的调谐电路。 该调谐电路包括具有第一晶体管（MN21）和可变电阻器单元（213）的电流产生单元（210），以及具有第二晶体管（MN22），电容器单元（223），电容器单元 一个可逆计数器（222）和一个选择单元（S4），用于选择升降计数器的控制路径以改变电阻或电容。

    TRACKING FILTER APPARATUS FOR WHEEL MONITORING SYSTEMS
    8.
    发明公开
    TRACKING FILTER APPARATUS FOR WHEEL MONITORING SYSTEMS 有权
    跟踪滤波器装置技术RADÜBERWACHUNGSSYSTEME

    公开(公告)号：EP2470382A1

    公开(公告)日：2012-07-04

    申请号：EP10771320.8

    申请日：2010-09-17

    申请人： Schrader Electronics Limited

    发明人： AINSWORTH, Christopher ,  STRAHAN, Samuel

    IPC分类号： B60C23/04 ,  H03H11/12

    CPC分类号： B60C23/0408 ,  H03H11/1291 ,  H03H2210/021 ,  H03H2210/043

    摘要： A wheel monitoring system that includes a tracking filter apparatus for tracking a signal that has a varying main frequency. The tracking filter apparatus has an adjustable filter and a filter controller arranged to measure the amplitude of the filtered signal and to compare amplitude against a reference value. The filter controller adjusts the cut off frequency of the filter if the measured amplitude differs from the reference value by an amount that exceeds a threshold value. The filter controller adjusts the cut off frequency such that the main frequency lies within the roll off region of the filter's frequency response. The system may be used to track signals that are produced by shock sensors in a wheel mounted monitoring device.