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    SIGNALVERARBEITUNGSEINRICHTUNG UND STEUEREINRICHTUNG
    1.
    发明公开
    SIGNALVERARBEITUNGSEINRICHTUNG UND STEUEREINRICHTUNG 审中-公开
    信号处理装置和控制装置

    公开(公告)号：EP3298689A1

    公开(公告)日：2018-03-28

    申请号：EP16715294.1

    申请日：2016-04-08

    申请人： Robert Bosch GmbH

    发明人： BRUCKHAUS, Tim

    IPC分类号： H03H1/02 ,  H03H7/42

    CPC分类号： H03H7/06 ,  G05F3/08 ,  H02P6/00 ,  H03H1/02 ,  H03H7/427

    摘要： The present invention discloses a signal processing device for processing a differential signal from a sensor at a prescribed signal frequency, having a positive signal input (5-1), which is couplable to a positive sensor output of the sensor, and a negative signal input (6-1), which is couplable to a negative sensor output of the sensor, having a positive signal output (7-1) and having a negative signal output (8-1), having a first frequency-dependent resistance (C1H) between the positive signal input (5-1) and the positive signal output (7-1) and having a second frequency-dependent resistance (C1L) between the negative signal input (6-1) and the negative signal output (8-1), wherein the first and second frequency-dependent resistances (C1H, C1L) are designed to allow electrical signals at the prescribed signal frequency to pass in approximately unattenuated fashion, having a first voltage divider (11), which is arranged at least in part in parallel with the first frequency-dependent resistance (C1H) and is designed to divide a voltage between the positive signal input (5-1) and the positive signal output (7-1) using a prescribed ratio, having a second voltage divider (12), which is arranged at least in part in parallel with the second frequency-dependent resistance (C1L) and is designed to divide a voltage between the negative signal input (6-1) and the negative signal output (8-1) using a prescribed ratio. Further, the present invention discloses a control device for an electric machine.

    Large time constant steering circuit and instrumentation amplifier implementing same
    3.
    发明公开
    Large time constant steering circuit and instrumentation amplifier implementing same 有权
    Steuerschaltung mit einer hohen Zeitkonstante

    公开(公告)号：EP2309644A1

    公开(公告)日：2011-04-13

    申请号：EP11151396.6

    申请日：2008-07-14

    申请人： IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

    发明人： Yaziciogly, Refet Firat ,  Merken, Patrick

    IPC分类号： H03H1/02 ,  H03K17/16 ,  H03H11/04 ,  H03F3/45 ,  A61B5/0428

    CPC分类号： H03H1/02 ,  A61B5/0428 ,  A61B5/0476 ,  H03F3/387 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/45479 ,  H03F2200/261 ,  H03F2203/45136 ,  H03F2203/45424 ,  H03F2203/45438 ,  H03F2203/45441

    摘要： Large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels, the circuit comprising an input node for receiving an input voltage, an output node for presenting an output voltage, a capacitive part connected at said output node for providing said output voltage and a resistive part connected between said input and output nodes for conducting a charging current from said input node to said capacitive part or a discharging current from said capacitive part to said input node depending on said input voltage. The resistive part comprises a semiconductor structure connectable between said input node and said capacitive part in such a way that the semiconductor structure remains in an off state irrespective of the input and output voltages and passes only leakage currents for charging or discharging said capacitive part.

    摘要翻译： 用于在至少两个离散电压电平之间缓慢地改变节点上的电压的大时间恒定转向电路，所述电路包括用于接收输入电压的输入节点，用于呈现输出电压的输出节点，连接在所述输出节点处的电容部分 用于提供所述输出电压和连接在所述输入和输出节点之间的电阻部分，用于根据所述输入电压从所述输入节点到所述电容部分的充电电流或从所述电容部分到所述输入节点的放电电流。 电阻部分包括可以在所述输入节点和所述电容部分之间连接的半导体结构，使得半导体结构保持在关闭状态，而与输入和输出电压无关，并且仅通过用于对所述电容部分充电或放电的泄漏电流。

    AN ELECTRONIC PART
    4.
    发明授权
    AN ELECTRONIC PART 有权
    电子元件

    公开(公告)号：EP1110312B1

    公开(公告)日：2009-03-25

    申请号：EP00947855.3

    申请日：2000-06-15

    申请人： NXP B.V.

    发明人： HORIE, Kenichi

    IPC分类号： H03H1/02

    CPC分类号： H01G4/35 ,  H01G4/40 ,  H03H1/02

    摘要： An electronic part enabling a further efficient attenuation of high-frequency noises is provided. The first dielectric paste is applied onto a PET film (30) to form a ceramic sheet (31) having a dielectric constant epsilon 1 thereupon; and ceramic films (22-3,22-4) are formed by applying the second dielectric paste on the ceramic sheet (31). Next, the pattern of the signal line (22-2) is printed by applying the conductive paste to the center of ceramic sheet (31) such that the right side (22-3a) of ceramic film (22-3) in the lengthwise direction and the left side (22-4a) of ceramic film (22-4) in the lengthwise direction are covered with the conductive paste; after that, further ceramic films (22-5,22-6) are formed such that the lateral ends (22-2d,22-2e) of the signal line (22-2) are sandwiched between the ceramic films (22-5,22-6;and22-3,22-4).

    COMPLEX LAMINATED CHIP ELEMENT
    5.
    发明公开
    COMPLEX LAMINATED CHIP ELEMENT 审中-公开
    复合层压芯片元件

    公开(公告)号：EP1654763A1

    公开(公告)日：2006-05-10

    申请号：EP04774129.3

    申请日：2004-07-15

    申请人： Innochips Technology Co., Ltd. ,  Park, In-Kil ,  Hwang, Soon-Ha ,  Kim, Duk-Hee

    发明人： Park, In-Kil ,  Hwang, Soon-Ha ,  Kim, Duk-Hee

    IPC分类号： H01L27/02

    CPC分类号： H01G4/40 ,  H01C1/148 ,  H01C7/008 ,  H01C7/18 ,  H01C13/02 ,  H01F17/0006 ,  H01F27/40 ,  H01F2017/0026 ,  H01G4/232 ,  H01G4/35 ,  H03H1/02 ,  H03H2001/0014 ,  H03H2001/0085 ,  H03H2001/0092

    摘要： The present invention relates to a laminated chip element which can be manufactured to have desired electric properties by combining various elements in accordance with the desired objectives. More p articularly, t he present invention relates to a laminated chip element which has superior high frequency properties and can be manufactured to control capacitance and/or inductance of the laminated chip element to a desired value. There is provided a laminated chip element, comprising at least one first sheet on which first and second conductive patterns are formed, the first and second conductive patterns being spaced apart from each other in a direction of both ends of the first sheet; and at least one second sheet on which a third conductive pattern is formed, the third conductive pattern being formed in a transverse direction of both the ends of the first sheet; wherein one ends of the first and second conductive patterns are connected to first and second external terminals, respectively, at least one end of the third conductive pattern is connected to a third external terminal, and the first and second sheets are laminated. There is also provided a laminated chip element, comprising: at least one first sheet on which a first conductive pattern is formed, the first conductive pattern consisting of first to third portions, the first and second portions being spaced apart from each other in a direction of both ends of the first sheet, the second portion connecting the first and second portions to each other to have a predetermined inductance; and at least one second sheet on which a second conductive pattern is formed in a transverse direction of both the ends of the first sheet; wherein the first and second portions are connected to first and second external terminals, respectively, at least one ends of the second conductive pattern is connected to a third external terminal, and the first and second sheets are laminated.

    Zero-IF-Konverter mit RC-Filter
    6.
    发明公开
    Zero-IF-Konverter mit RC-Filter 审中-公开

    公开(公告)号：EP1022851A2

    公开(公告)日：2000-07-26

    申请号：EP00200181.6

    申请日：2000-01-17

    申请人： Philips Corporate Intellectual Property GmbH ,  Koninklijke Philips Electronics N.V.

    发明人： Löbl, Hans Peter ,  van Oppen, Paul Henri Maria ,  Rijks, Theo ,  Klee, Mareike ,  Doodeman, Gert

    IPC分类号： H03H7/06

    CPC分类号： H03H1/02

    摘要： Ein Zero-IF-Konverter, insbesondere für digitale Satellitenempfänger, mit einem Dünnschichtbauteil mit mindestens zwei RC-Filtern mit jeweils einem Widerstand und einem Kondensator mit jeweils einer Unterelektrode, einer Oberelektrode und einem Dielektrikum, bei dem die RC-Filter auf einem gemeinsamen Substrat angeordnet sind, zeichnet sich durch eine konstante Amplituden- und Phasenrelation zwischen den Basis-Signalen I und Q aus.

    摘要翻译： 零中频转换器包括具有至少两个RC滤波器的薄膜器件。 每个滤波器由一个电阻和一个电容组成。 RC滤波器布置在公共基板上。 至少一个RC滤波器是分布式RC滤波器或离散RC滤波器。 分布式RC滤波器的上电极（1）和下电极（3）可以是电阻的，具有相关联的电介质。 至少一个RC滤波器可以是具有陷波阻抗的陷波滤波器。 对于具有至少两个RC滤波器的薄膜器件，包括独立声明。

    High-precision calibration circuit calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
    9.
    发明公开
    High-precision calibration circuit calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance 有权
    用于校准集成电路的可调电容的时间常数依赖于电容高精度校准电路

    公开(公告)号：EP1962420A1

    公开(公告)日：2008-08-27

    申请号：EP07425099.4

    申请日：2007-02-23

    申请人： STMicroelectronics S.r.l.

    发明人： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Nicollini, Germano

    IPC分类号： H03H1/02 ,  H03H7/01

    CPC分类号： H03H7/0153 ,  H03H1/02 ,  H03H2210/021 ,  H03H2210/043

    摘要： A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitance ((C var (REG_BUS)) and including a calibration loop (U_CV, CMP, TG_SAR), suitable to carry out a calibration cycle (C_LOOP) in several sequential steps (St_1, ..., St4), comprising:
    - a controllable capacitance unit (U_CV) suitable to receive a control signal (SAR_BUS) at the beginning of a calibration step and including an array of switched capacitors (C_AR1) that can be selectively activated by the control signal to be connected to a first common node (N_u) having, at the end of an integration interval (P2), a voltage value (VRC) depending on the total capacitance value of the activated capacitors;
    - an assessment unit (CMP) suitable to compare this voltage value (VRC) with a reference voltage to output a logic signal (OUT_CMP) that, based on the comparison result can be subjected to a transition between first and second logic levels;
    - a control and timing unit (TG_SAR) suitable to receive the logic signal (OUT_CMP) and to change the control signal (SAR_BUS) based thereon, in order to carry out a subsequent calibration step,

    characterized in that
    in said calibration step is provided, at the end of said integration interval (P2) a comparison interval (P3) of a preset duration, which allows a transition (tl,t4) of the logic signal (OUT_CMP) to occur prior to the beginning of said consecutive calibration step.

    摘要翻译： 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容（C（VAR（REG_BUS））和包括校准环路（U_CV，CMP，TG_SAR），适合在几个连续的步骤来进行校准周期（C_LOOP）（ST_1，...，圣4 ），包括： - 一个可控电容单元（U_CV）适合于在校准步骤的开始接收的控制信号（SAR_BUS），并在开关电容器阵列（C_AR1）包括也可以由控制信号被选择性地激活以连接 到第一公共节点（N_u），其具有，在一个积分区间（P2）结束时，一个电压值（VRC）根据激活的电容器的总电容值; - 评估单元（CMP）适合于比较该电压 值（VRC）与参考 ENCE电压以输出逻辑信号（OUT_CMP），基于该比较结果可以进行第一和第二逻辑电平之间的转变; - 控制和定时单元（TG_SAR）适合于接收所述逻辑信号（OUT_CMP）和改变控制信号（SAR_BUS）基于其，以便进行随后的校准步骤中，在“那个”中设置的所述校准步骤为特征的， 在逻辑信号（OUT_CMP）的所述积分间隔（P2）在预设持续时间的比较区间（P3），它允许一个过渡（TL，T4）的端部之前，所述连续校准步骤的开始时发生。