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    A BUS DRIVER CIRCUIT CONFIGURED TO PARTIALLY DISCHARGE A BUS CONDUCTOR TO DECREASE LINE TO LINE COUPLING CAPACITANCE
    2.
    发明公开
    A BUS DRIVER CIRCUIT CONFIGURED TO PARTIALLY DISCHARGE A BUS CONDUCTOR TO DECREASE LINE TO LINE COUPLING CAPACITANCE 失效
    公共汽车线路局部放电巴士司机异径接头线之间

    公开(公告)号：EP0867071A1

    公开(公告)日：1998-09-30

    申请号：EP96936489.0

    申请日：1996-10-15

    申请人： Advanced Micro Devices, Inc.

    发明人： GEISLER, Joseph, P.

    IPC分类号： G06F3 ,  H03K17 ,  H03K19

    CPC分类号： H03K19/01728 ,  H03K19/00361

    摘要： A driver circuit is provided which unconditionally discharges a bus conductor during clock cycles in which the driver circuit is transmitting a value. The unconditional discharge occurs during a first drive phase of the logic drive state. During a second drive phase, the driver circuit either charges or continues to discharge the conductor based on the data value being transmitted. Since the conductors are transitioning in the same direction at approximately the same rate, line to line coupling is virtually non-existent during the first drive phase. By partially discharging bus conductors during the first drive phase, transition speed is increased to the point at which a receiving circuit senses the transmitted value. Effectively, the line-to-line coupling which would have occurred during the first drive phase is endured during the second drive phase, when certain conductors may be recharged. Shifting the coupling to the second drive phase results in the more rapid transition of the bus signals during the first drive phase.

    High speed output buffer unit preliminarily shifting output voltage level
    3.
    发明公开
    High speed output buffer unit preliminarily shifting output voltage level 失效
    Schnelle Ausgangspufferschaltung mit Vorverschiebung des Ausgangsspannungspegels。

    公开(公告)号：EP0471289A1

    公开(公告)日：1992-02-19

    申请号：EP91113307.2

    申请日：1991-08-08

    申请人： NEC CORPORATION

    发明人： Goto, Hiroyuki, c/o NEC Corporation

    IPC分类号： G11C7/00 ,  H03K19/017

    CPC分类号： G11C7/1048 ,  G11C7/1051 ,  H03K19/01728

    摘要： An output buffer unit comprises a controlling circuit (31 a) responsive to an input data signal (DB) for producing a first controlling signal and a driving circuit (31 b) implemented by a series combination of a p-channel type field effect transistor (2a) and an n-channel type field effect transistor (2b) complementarily shifted between one and off states for producing an output data signal, and a shifting circuit (31 e) is provided in association with the driving circuit so as to transfer a second controlling signal produced from the previous output data signal stored in a latching circuit (31d) to the field effect transistors (2a/2b) for preliminarily changing the voltage level of an output data signal and, thereafter, to transfer the first controlling signal to the field effect transistors (2a/2b) for finally determining the voltage level of the next output data signal so that the voltage level at the output node of the driving circuit quickly crosses over a discriminating level of data bit.

    摘要翻译： 输出缓冲器单元包括响应于用于产生第一控制信号的输入数据信号（DB）和由p沟道型场效应晶体管（2a）的串联组合实现的驱动电路（31b）的控制电路（31a） 和n沟道型场效应晶体管（2b）在一个和一个关闭状态之间互补地移动以产生输出数据信号，并且与驱动电路相关联地提供移位电路（31e），以便传送产生的第二控制信号 从存储在锁存电路（31d）中的先前输出数据信号输出到用于预先改变输出数据信号的电压电平的场效应晶体管（2a / 2b），然后将第一控制信号传送到场效应晶体管 （2a / 2b），用于最终确定下一个输出数据信号的电压电平，使得驱动电路的输出节点处的电压电平快速跨过数据的识别电平 一点点。

    Boosting circuits
    6.
    发明公开
    Boosting circuits 失效
    Spannungserhöhungsschaltungen。

    公开(公告)号：EP0030813A2

    公开(公告)日：1981-06-24

    申请号：EP80304344.7

    申请日：1980-12-03

    申请人： FUJITSU LIMITED

    发明人： Nakano, Masao ,  Baba, Fumio ,  Mochizuki, Hirohiko

    IPC分类号： H03K5/02

    CPC分类号： H02M3/07 ,  G11C5/145 ,  G11C11/4076 ,  G11C11/4085 ,  H03K5/00 ,  H03K19/00 ,  H03K19/01707 ,  H03K19/01728 ,  H03K19/096

    摘要： An output clock signal of a driver 11 charges load capacitance CLto a specific voltage.
    Boosting circuit 21 has a boosting capacitance CB one end 13 of which is arranged for receiving a clock signal φ, delayed from the output clock signal of driver 11. A charging circuit for CB comprises voltage supply line 24 and transistor Q3, so CB does not load driver 11. A gate circuit comprising transistor Q1 is provided between boosting capacitor CB and the load capacitance CL. A gate control circuit opens transistor Q1, so that charges can pass from CB to CL to boost the voltage of CL, when a clock signal φ is received. When CL is being discharged the gate control circuit closes transistor Q1. The gate control circuit includes an auxiliary capacitor CG, a transistor Q2 and voltage line 24. CG is charged from the driver 11 through Q2 and when clock signal A is received the voltage of CG, which is applied to the gate of Q1, is raised to open Q1.

    摘要翻译： 驱动器11的输出时钟信号将负载电容CL充电到特定电压。 升压电路21具有升压电容CB，其一端13被布置为接收从驱动器11的输出时钟信号延迟的时钟信号phi。用于CB的充电电路包括电压供给线24和晶体管Q3 因此CB不加载驱动器11.包括晶体管Q1的门电路设置在升压电容器CB和负载电容CL之间。 门控制电路打开晶体管Q1，使得当接收到时钟信号时，电荷可以从CB传递到CL以升高CL的电压。 当CL放电时，门控电路关闭晶体管Q1。 门控电路包括辅助电容器CG，晶体管Q2和电压线24.从驱动器11通过Q2对CG进行充电，并且当接收到时钟信号phi时，施加到Q1的栅极的CG的电压被升高 打开Q1。

    LOW-POWER WIDEBAND ASYNCHRONOUS BINARY PHASE SHIFT KEYING DEMODULATION CIRCUIT USING PRIMARY SIDEBAND FILTERS ALIGNED WITH PHASE OF 180° AND HAVING REDUCED JITTER ACCORDING TO PHASE OF SIDEBAND DIFFERENTIAL OUTPUT COMPARATORS
    7.
    发明公开
    LOW-POWER WIDEBAND ASYNCHRONOUS BINARY PHASE SHIFT KEYING DEMODULATION CIRCUIT USING PRIMARY SIDEBAND FILTERS ALIGNED WITH PHASE OF 180° AND HAVING REDUCED JITTER ACCORDING TO PHASE OF SIDEBAND DIFFERENTIAL OUTPUT COMPARATORS 审中-公开
    低功率宽带异步二值相移键控解调电路使用初级侧带滤波器进行180°相位调整，并根据边带差分输出比较器的相位进行降低抖动

    公开(公告)号：EP3208984A1

    公开(公告)日：2017-08-23

    申请号：EP15850547.9

    申请日：2015-10-15

    申请人： Wilkerson, Benjamin P.

    发明人： Wilkerson, Benjamin P.

    IPC分类号： H04L27/233 ,  H03H17/00

    CPC分类号： H04L27/233 ,  H03K5/2481 ,  H03K19/01728 ,  H03K19/01855 ,  H03K19/0963 ,  H04L7/0278 ,  H04L27/2331 ,  H04L27/2334 ,  H04L27/2335 ,  H04W4/80

    摘要： An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit for separating a modulated signal into an upper sideband and a lower sideband using a primary high pass filter, which has a carrier frequency as the cutoff frequency thereof, and a primary low pass filter and digitalizing the same into a positive phase and a negative phase such that, in connection with a digital output from a lower sideband comparator and a digital output from an upper sideband comparator, signals with opposite phases are compared at the same ascending edge and at the same descending edge between a symbol edge and another symbol edge, respectively, thereby reducing jitter to the largest extent, improving the yield ratio, and outputting lower sideband digital signals and upper sideband digital signals, the lower sideband digital signals having been delayed by the 1/4 frequency of the carrier frequency; a data demodulation unit for generating a first symbol edge signal detected by aligning the phase difference between a delayed lower sideband positive-phase digital signal and an upper sideband negative-phase digital signal to be 180° and generating a second symbol edge signal detected by aligning the phase difference between a delayed lower sideband negative-phase digital signal and an upper sideband positive-phase digital signal to be 180°, the data demodulation unit overlapping the first symbol edge signal and the second symbol edge signal through an AND gate, thereby reducing the glitch and generating a symbol edge clock, which has no glitch, through a deglitch filter, the data demodulation unit synchronizing the delayed lower sideband positive-phase digital signal with a descending edge of the symbol edge signal, thereby demodulating data; and a data clock restoration unit for generating a data clock using the delayed lower sideband positive-phase digital signal and the demodulated data signal.

    摘要翻译： 本发明的一个实施例涉及一种低功率宽带异步BPSK解调方法及其电路的配置。 结合BPSK解调电路的配置，可以提供一种低功率宽带异步二相移键控解调电路，包括：边带分离和下边带信号延迟单元，用于将调制信号分离成上边带和下边带 使用具有作为其截止频率的载波频率的主高通滤波器和主低通滤波器并将其数字化成正相位和负相位，使得结合来自下边带的数字输出 比较器和来自上边带比较器的数字输出，在符号边缘和另一符号边缘之间的相同上升边缘和相同下降边缘处分别比较具有相反相位的信号，从而最大程度地减小抖动，提高产量 比例，并输出下边带数字信号和上边带数字信号，下边带数字符号 已经延迟了载波频率的1/4频率; 数据解调单元，用于生成通过将延迟的下边带正相数字信号和上边带反相数字信号之间的相位差对齐为180°而检测的第一码元边缘信号，并生成通过对准检测到的第二码元边缘信号 延迟的下边带反相数字信号和上边带正相数字信号之间的相位差为180°，数据解调单元通过与门重叠第一符号边缘信号和第二符号边缘信号，由此减小 所述数据解调单元将所述延迟的下边带正相位数字信号与所述符号边沿信号的下降沿同步，从而对数据进行解调;所述数据解调单元通过去毛刺滤波器生成没有毛刺的符号边沿时钟， 以及数据时钟恢复单元，用于使用延迟的下边带正相数字信号和解调数据信号来产生数据时钟。