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公开(公告)号：EP2197110A1
公开(公告)日：2010-06-16
申请号：EP09014884.2
申请日：2009-12-01
CPC分类号： H03K3/0315 , H03K2005/00293
摘要： Beschrieben und dargestellt ist eine Schaltungsanordnung zur Erzeugung kurzer elektrischer Impulse.
Erfindungsgemäß ist die Schaltungsanordnung gekennzeichnet durch ein Logikgatter (1) mit einer sehr kurzen Gatterlaufzeit und weiter dadurch, daß dem Ansteuereingang (2) des Logikgatters (1) als Ansteuersignal ein Taktsignal zugeführt wird und das durch das Ansteuersignal generierte, am Ausgang (3) des Logikgatters (1) oder an einem Ausgang (3 oder 4) des Logikgatters (1) oder an beiden Ausgängen (3 und 4) des Logikgatters (1) entstehende Ausgangssignal als zu erzeugender kurzer elektrischer Impuls zur Verfügung stehen.摘要翻译： 该装置具有形成为具有清零输入（5）和预设输入（6）的快速D-触发器的逻辑门（1），并且具有非常短的延迟时间。 时钟信号作为控制信号提供给逻辑门的控制输入（2）。 在逻辑门的输出端（3,4）或通过控制信号的一个输出端产生输出信号作为要产生的短电脉冲。 脉冲整形器网络存在于逻辑门输出的下游，用于缩短产生的电脉冲的脉冲持续时间。 逻辑门从与门，或门，NAND门，EXOR门或INVERTER门选择。
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公开(公告)号：EP3211822A1
公开(公告)日：2017-08-30
申请号：EP17167127.4
申请日：2014-03-20
IPC分类号： H04L7/033 , H03K5/1252 , H03K5/1534 , H04L25/49 , H04L25/14
CPC分类号： H04L7/0087 , H03K3/017 , H03K5/13 , H03K5/133 , H03K5/134 , H03K5/14 , H03K5/153 , H03K5/1534 , H03K19/00 , H03K2005/00293 , H03L7/081 , H04L7/0037 , H04L7/033 , H04L7/0331
摘要： A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.
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公开(公告)号：EP0998041A3
公开(公告)日：2004-11-24
申请号：EP99121427.1
申请日：1999-10-27
发明人： Yoshikawa, Kiyoshi
IPC分类号： H03K5/13
CPC分类号： G01R31/31922 , H03H11/26 , H03K5/04 , H03K5/133 , H03K5/1534 , H03K2005/00026 , H03K2005/00156 , H03K2005/00293
摘要： A variable delay circuit comprising a positive logic variable delay circuit (1) for delaying an edge of a signal input through an input terminal and a negative logic variable delay circuit (2) for delaying an edge of a signal input through an input terminal, in which only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit (1) and all the edges of a signal supplied from the negative logic variable delay circuit (2).
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4.发明公开MULTI-WIRE OPEN-DRAIN LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING 有权ÜBERGÄGNENVON DATENSYSMBOLEN的MEHRDRAHTIGE OPEN-DRAIN VERBINDUNG MIT TAKTUNG BERUHEND
公开(公告)号：EP2976853A1
公开(公告)日：2016-01-27
申请号：EP14723593.1
申请日：2014-03-20
CPC分类号： H04L7/0087 , H03K3/017 , H03K5/13 , H03K5/133 , H03K5/134 , H03K5/14 , H03K5/153 , H03K5/1534 , H03K19/00 , H03K2005/00293 , H03L7/081 , H04L7/0037 , H04L7/033 , H04L7/0331
摘要： A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.
摘要翻译： 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与针对第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预先配置的第一和/或第二间隔。
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公开(公告)号：EP1120914A1
公开(公告)日：2001-08-01
申请号：EP00128180.7
申请日：2000-12-21
发明人： Kuhne, Sebastian
IPC分类号： H03K5/1534 , H03K5/13 , H03K5/06
CPC分类号： H03K5/06 , H03K5/133 , H03K5/1534 , H03K2005/00293
摘要： Die Erfindung betrifft eine Impulserzeugerschaltung, insbesondere zur Verwendung in bzw. für integrierte(n) Schaltungen, die in üblicher Weise eine ungerade Anzahl von in Reihe geschalteten Invertiergliedern (11, 15, 17) ein logisches Verknüpfungsglied (16) und ein Verzögerungsglied (12) aufweist. Eine erfindungsgemäß vorgesehene Zwischenspeicherschaltung (13,14) sorgt dafür, dass auch bei einem Eingangssignal (A) sehr kurzer Dauer eine minimale Impulsdauer des auf das Eingangssignal (A) erzeugten Ausgangsimpulses (0) garantiert ist.
摘要翻译： 脉冲发生器电路，特别是用于或用于集成电路，其以通常的方式具有串联连接的多个反相元件，逻辑组合元件和延迟元件。 根据本发明提供的缓冲电路确保即使在非常短的持续时间的输入信号的情况下也能确保响应于输入信号产生的输出脉冲的最小脉冲长度。
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公开(公告)号：EP3182589A1
公开(公告)日：2017-06-21
申请号：EP15200708
申请日：2015-12-17
申请人： IMEC VZW
发明人： CRANINCKX JAN , INGELS MARK
CPC分类号： H03K5/131 , H03K2005/00058 , H03K2005/00071 , H03K2005/0028 , H03K2005/00293
摘要： The present invention relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit comprises - a driver circuit (10) arranged to receive a signal (11) and to output a delayed signal (12) and comprising a variable load (20) arranged for adding delay to said signal, - a control circuit (30) arranged to receive the signal (12) and to control the variable load of the driver circuit based on a current state of the signal and on a control signal (external) indicative of an amount of delay to be added to the signal in the current state.
摘要翻译： 延迟控制电路技术领域本发明涉及延迟控制电路，其被布置用于将延迟添加到信号。 该延迟控制电路包括： - 驱动器电路（10），其被布置为接收信号（11）并且输出延迟信号（12）并且包括被布置用于将延迟添加到所述信号的可变负载（20）， - 控制电路 30），其被布置成接收信号（12）并且基于信号的当前状态和控制信号（外部）来控制驱动器电路的可变负载，所述控制信号指示要添加到 当前状态。
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7.发明公开Clock pulse generator apparatus with reduced jitter clock phase 审中-公开Taktimpulserzeugungsgerätmit reduziertem Phasenzittern
公开(公告)号：EP1538752A1
公开(公告)日：2005-06-08
申请号：EP03292967.1
申请日：2003-11-28
发明人： Ihs, Hassan
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K5/06 , H03K2005/00097 , H03K2005/00293 , H03L7/0805 , H03L7/0812 , H03M3/372 , H03M3/424 , H03M3/438 , H03M3/458 , H03M3/50
摘要： Clock pulse generator apparatus comprising a clock pulse generator (CLK) for generating a train of primary clock pulses having leading and trailing edges. A delay line (14) produces a train of delayed clock pulses (CLK_D) presenting delayed edges whose timing relative to corresponding edges of the primary clock pulses (CLK) is defined by the delay line. A logic circuit (15) produces a train of combined clock pulses (CLK_JF) presenting leading and trailing edges defined alternately by one of the delayed edges and the corresponding edge of the primary clock pulse, so that the combined clock pulses comprise active clock phases (ACP) having widths defined by the delay line; the variability of the widths of the active clock phases (ACP) is smaller than the variability of the positions of the leading and trailing edges of the primary clock pulses (CLK). The active clock phases (ACP) alternate with non-active clock phases (NACP) whose widths vary as a function of variation in the positions of the primary clock pulses (CLK) and absord those variations. The delay line (14) comprises a series of cascaded, substantially identical delay elements (16). A temperature and process variation circuit (22) is also described.
Application especially to continuous-time sigma-delta converters where a critical integrator (2; 10) integrates a signal over periods of time defined by the widths of the active clock phases (ACP).摘要翻译： 时钟脉冲发生器装置包括用于产生具有前沿和后沿的主时钟脉冲串的时钟脉冲发生器（CLK）。 延迟线（14）产生延迟时钟脉冲序列（CLK_D），其延迟边缘的相对于主时钟脉冲（CLK）的相应边缘的定时由延迟线限定。 逻辑电路（15）产生一系列组合的时钟脉冲（CLK_JF），其显示由主时钟脉冲的延迟边缘和对应边缘之一交替地定义的前沿和后沿，使得组合的时钟脉冲包括有源时钟相位 ACP）具有由延迟线限定的宽度; 有源时钟相位（ACP）的宽度的变化小于主时钟脉冲（CLK）的前沿和后沿的位置的可变性。 有源时钟相位（ACP）与非主动时钟相位（NACP）交替，其宽度随着主时钟脉冲（CLK）的位置变化而变化，并排除这些变化。 延迟线（14）包括一系列级联的，基本相同的延迟元件（16）。 还描述了温度和过程变化电路（22）。 特别适用于连续时间Σ-Δ转换器，其中临界积分器（2; 10）在由有效时钟相位（ACP）的宽度限定的时间段内积分信号。
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公开(公告)号：EP0998041A2
公开(公告)日：2000-05-03
申请号：EP99121427.1
申请日：1999-10-27
申请人： NEC Corporation
发明人： Yoshikawa, Kiyoshi
IPC分类号： H03K5/13
CPC分类号： G01R31/31922 , H03H11/26 , H03K5/04 , H03K5/133 , H03K5/1534 , H03K2005/00026 , H03K2005/00156 , H03K2005/00293
摘要： A variable delay circuit comprising a positive logic variable delay circuit (1) for delaying an edge of a signal input through an input terminal and a negative logic variable delay circuit (2) for delaying an edge of a signal input through an input terminal, in which only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit (1) and all the edges of a signal supplied from the negative logic variable delay circuit (2).
摘要翻译： 一种可变延迟电路，包括用于延迟通过输入端子输入的信号的边沿的负逻辑可变延迟电路（1）和用于延迟通过输入端子输入的信号的边沿的负逻辑可变延迟电路（2）， 从正逻辑可变延迟电路（1）提供的信号的全部边缘和从负逻辑可变延迟电路（2）提供的信号的所有边缘提取仅根据设定时间延迟的边沿。
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9.发明授权
公开(公告)号：EP2976853B1
公开(公告)日：2017-06-21
申请号：EP14723593.1
申请日：2014-03-20
CPC分类号： H04L7/0087 , H03K3/017 , H03K5/13 , H03K5/133 , H03K5/134 , H03K5/14 , H03K5/153 , H03K5/1534 , H03K19/00 , H03K2005/00293 , H03L7/081 , H04L7/0037 , H04L7/033 , H04L7/0331
摘要： A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.
摘要翻译： 描述了一种方法，一种装置和一种计算机程序产品。 该设备通过确定从多线开路漏极链路接收的信号中的转变，产生用于从多线漏极开路链路接收数据的接收时钟信号，响应于该转变产生时钟脉冲，延迟时钟脉冲 如果所述转变处于第一方向，则通过预先配置的第一间隔，并且如果所述转变处于第二方向，则将所述时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间配置预先配置的第一和/或第二间隔，并且可以通过测量与针对第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准。
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公开(公告)号：EP2392008A1
公开(公告)日：2011-12-07
申请号：EP10703396.1
申请日：2010-02-02
CPC分类号： G11C7/22 , G11C7/04 , G11C16/12 , H03K2005/00293
摘要： In a particular embodiment, a device (102) includes a reference voltage circuit (110) to generate a controlled voltage. The device includes a frequency circuit (106) configured to generate a frequency output signal (328) having a pre-set frequency and a counter (304) to generate a count signal (310) based on the pre-set frequency. The device also includes a delay circuit (306) coupled to receive the count signal and to produce a delayed digital output signal (312) and a latch (320) to generate a pulse (130). The pulse has a first edge (132) responsive to a write command and a trailing edge (134) formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.
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