利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

47 条记录 (耗时 0.016 秒)

    Subrange-type A/D converter
    2.
    发明公开
    Subrange-type A/D converter 失效
    Analoger Digitalwandler mit zwei Arbeitsbereichen。

    公开(公告)号：EP0526913A2

    公开(公告)日：1993-02-10

    申请号：EP92117914.9

    申请日：1988-09-13

    申请人： NIPPON HOSO KYOKAI

    发明人： Ninomiya, Yuichi ,  Iwadate, Yuichi

    IPC分类号： H04N7/12 ,  H03M1/14 ,  H04N7/24

    CPC分类号： H03M1/069 ,  H03M1/145 ,  H04N5/211 ,  H04N7/0152 ,  H04N7/125 ,  H04N19/59

    摘要： The subrange-type A/D converter includes A/D converters in multiple stages (204, 212), with their driving clock frequencies being in certain relationship so that they are used commonly for the A/D conversion of the high definition television signal and the A/D conversion of a test signal for detecting the transmission characteristics.

    摘要翻译： 子类型A / D转换器包括多级（204,212）的A / D转换器，其驱动时钟频率处于一定关系，以便它们被共同用于高分辨率电视信号的A / D转换， 用于检测传输特性的测试信号的A / D转换。

    Calibration apparatus for systems such as analog to digital converters
    3.
    发明公开
    Calibration apparatus for systems such as analog to digital converters 失效
    用于数字转换器模拟的系统的校准装置

    公开(公告)号：EP0142298A3

    公开(公告)日：1986-12-10

    申请号：EP84307269

    申请日：1984-10-22

    申请人： JOHN FLUKE MFG. CO., INC.

    发明人： Duryee, Peter Schuyler ,  Anholm, John Milford, Jr.

    IPC分类号： H03M01/40

    CPC分类号： H03M1/069 ,  H03M1/403

    摘要： A calibration circuit for a recirculation of remainder analog-to-digital (A/D) converter heuristically solves a multi- plevariable conversion equation. Input analog calibration and analog reference signals are compared in a comparator (40), and when the two signals have a predetermined relationship, the comparator (40) generates an indicator signal. A microprocessor (15) determines (a) a first pattern of digital reference signals that, together with digital calibration signals generated by the microprocessor, causes the comparator (40) to generate the indicator signal and (b) a second pattern of digital reference signalsthat,together with the inputanalog calibration signals, causes the comparator to generate the indicator signal. The difference between the first and second patterns of digital reference signals is stored as conversion coefficients.

    DSP receiver with high speed low BER ADC
    4.
    发明公开
    DSP receiver with high speed low BER ADC 审中-公开
    DSP-Empfängermit einem hochgeschwindigkeits-ADW mit geringer Bitfehlerquote

    公开(公告)号：EP2722990A2

    公开(公告)日：2014-04-23

    申请号：EP13004704.6

    申请日：2013-09-27

    申请人： Broadcom Corporation

    发明人： Zhang, Bo ,  Nazemi, Ali ,  Momtaz, Afshin ,  Mahmoud, Ahmadi ,  Zhang, Heng ,  Hassan, Maarefi

    IPC分类号： H03M1/14 ,  H03M1/36

    CPC分类号： H03M1/1009 ,  H03M1/069 ,  H03M1/1023 ,  H03M1/141 ,  H03M1/188 ,  H03M1/361

    摘要： Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

    摘要翻译： 描述了具有模数转换器（ADC）的DSP接收器的方法和装置，其具有高速度，低BER性能，低功率和面积要求。 通过解决常规瓶颈，多路径ADC配置的速度提高。 通过集成校准和错误检测和校正（如分布式偏移校准和冗余比较器）可提高ADC性能。 通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量几乎减半，功率和面积要求大大降低。

    High resolution overlapping bit segmented dac
    5.
    发明公开
    High resolution overlapping bit segmented dac 审中-公开
    Segmentierter Digital-Analogwandler mithochauflösendemÜberlappungsbit

    公开(公告)号：EP2328274A1

    公开(公告)日：2011-06-01

    申请号：EP10192277.1

    申请日：2010-11-23

    申请人： NXP B.V.

    发明人： Mahooti, Kevin ,  Bo, He ,  Hao, Meng ,  Lee, Johnny ,  Feng, Tian Jie ,  Yang, Rui

    IPC分类号： H03M1/68 ,  H03M1/06

    CPC分类号： H03M1/069 ,  H03M1/0617 ,  H03M1/687

    摘要： A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and, in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.

    摘要翻译： 控制器接收M位输入，作为响应，生成S位上限二进制数据馈送S位高范围DAC和馈送R位低范围DAC的R位下限范围数据。 控制器检测M位输入中的转换点，并作为响应，将转移数据添加到等于S位数据的至少一个最低有效位的S位数据，并从R位数据中减去一个值 等于过渡数据。 在R位数据的满量程值处避免这种转变的点处检测和添加转换点和转移数据。

    Analog/digital conversion with adjustable thresholds
    7.
    发明公开
    Analog/digital conversion with adjustable thresholds 有权
    Analog / Digital-Wandler mit einstellbaren Schwellwerten

    公开(公告)号：EP1633050A1

    公开(公告)日：2006-03-08

    申请号：EP04292152.8

    申请日：2004-09-07

    申请人： ALCATEL

    发明人： Franz, Bernd ,  Buchali, Fred ,  Bülow, Henning

    IPC分类号： H03M1/00

    CPC分类号： H03M1/186 ,  H03M1/069

    摘要： A device for receiving a distorted signal, in particular an optical signal converted by an opto/electrical converter, comprises an analog/digital converter (1) with adjustable thresholds and a Viterbi equalizer (10). The device further comprises a histogram estimator (13) for determining a probability density function of the distorted signal and a threshold estimator (4) for dynamically adjusting at least one threshold of the analog/digital converter (1) in an overlap region of a first signal amplitude attributed to a first symbol (σ 10 , X 10 ) and a second signal amplitude attributed to a second symbol (σ 11 , X 11 ) of the probability density function.

    摘要翻译： 用于接收失真信号的装置，特别是由光/电转换器转换的光信号，包括具有可调节阈值的模拟/数字转换器（1）和维特比均衡器（10）。 所述装置还包括用于确定失真信号的概率密度函数的直方图估计器（13）和用于在第一个信号的重叠区域中动态地调整模/数转换器（1）的至少一个阈值的阈值估计器（4） 归因于第一符号（10，X 10）的信号幅度和归因于概率密度函数的第二符号（×11，X 11）的第二信号幅度。

    ANALOG-TO-DIGITAL CONVERSION WITH MULTIPLE CHARGE REDISTRIBUTION CONVERSIONS
    9.
    发明公开
    ANALOG-TO-DIGITAL CONVERSION WITH MULTIPLE CHARGE REDISTRIBUTION CONVERSIONS 失效
    具有多电荷再分配反应的模拟 - 数字转换

    公开(公告)号：EP0809889A2

    公开(公告)日：1997-12-03

    申请号：EP96907055.0

    申请日：1996-02-15

    申请人： ANALOG DEVICES, INCORPORATED

    发明人： COTTER, Martin, G. ,  GARAVAN, Patrick, J.

    IPC分类号： H03M1

    CPC分类号： H03M1/069 ,  H03M1/145 ,  H03M1/466 ,  H03M1/804

    摘要： Performing a coarse conversion of an analog signal to a coarse digital representation using a first analog-to-digital converter, transferring the coarse representation to a second converter, and performing a fine analog-to-digital conversion of the signal using the coarse representation as a starting value for a fine digital representation. The fine conversion can include a redundant portion that can be used to correct a mismatch between the coarse and fine conversions, and this correction can operate according to a combinatorial transfer function. The fine conversion may include switching from a coarse reference to a fine reference after transferring the coarse representation. The fine conversion can also include comparing an amount of charge in a sampling capacitor after performing the coarse conversion. Also disclosed is converting an analog signal to a digital representation having a first resolution level, adjusting a bandwidth of the converter circuit, and then continuing to convert the analog signal to a second, higher resolution level. The adjusting can include adjusting a bandwidth of a comparison circuit. Further disclosed is evaluating the amount of charge stored in a second sampling capacitor while tracking an analog signal with the first sampling capacitor. The amount of charge stored in the first capacitor is evaluated while tracking the signal with the second capacitor. Evaluating the amount of charge in the first capacitor can include comparing performed in part by a first comparator input stage, evaluating the amount of charge in the second capacitor can include comparing performed in part by a second comparator input stage. Analog-to-digital conversion circuitry can be multiplexed between the sampling capacitors.