公开(公告)号：EP2701062A1

公开(公告)日：2014-02-26

申请号：EP12773634.6

申请日：2012-04-18

申请人： NEC Corporation

发明人： YAMAGUCHI, Keisuke

IPC分类号： G06F9/46 ,  G06F9/50

CPC分类号： G06F9/45558 ,  G06F9/45533 ,  G06F9/5077 ,  G06F11/1484 ,  G06F2009/4557 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

摘要： In a virtual machine system, an arrangement of virtual machines, which has fault tolerance, is performed. A virtual machine managing apparatus (100) includes a similar group generating unit (102) and an arrangement restriction generating unit (105). The similar group generating unit (102) generates a group of virtual machines (201) having a similarity relationship which indicates that performance values of virtual machines at each timing are approximately the same, out of plural virtual machines. The arrangement restriction generating unit (105) outputs the group of virtual machines (201) having the similarity relationship as a distributed-arrangement restriction indicating a group of virtual machines (201) to be arranged on different processing apparatuses (200) among plural processing apparatuses (200) carrying out processes of the virtual machines (201).

公开(公告)号：EP2325747A3

公开(公告)日：2012-08-08

申请号：EP10251636.6

申请日：2010-09-23

申请人： Intel Corporation

发明人： Chinya, Gautham N. ,  Wang, Hong ,  Schuchman, Ethan

IPC分类号： G06F9/455

CPC分类号： G06F9/45533 ,  Y02D10/26 ,  Y02D10/28

摘要： A system to prototype a system-on-chip design is presented. In one embodiment, the system includes an electronic board comprising a logic device programmable to emulate system components. The system further comprises a processor to execute a virtual machine monitor which redirects an input/output request to the system components via an interconnect.

摘要翻译： 介绍了系统级芯片设计原型的系统。 在一个实施例中，该系统包括电子板，其包括可编程以模拟系统组件的逻辑设备。 该系统还包括处理器，用于执行虚拟机监视器，其经由互连将输入/输出请求重定向到系统组件。

公开(公告)号：EP2325747A2

公开(公告)日：2011-05-25

申请号：EP10251636.6

申请日：2010-09-23

申请人： Intel Corporation

发明人： Chinya, Gautham N. ,  Wang, Hong ,  Schuchman, Ethan

IPC分类号： G06F9/455

CPC分类号： G06F9/45533 ,  Y02D10/26 ,  Y02D10/28

摘要： A system to prototype a system-on-chip design is presented. In one embodiment, the system includes an electronic board comprising a logic device programmable to emulate system components. The system further comprises a processor to execute a virtual machine monitor which redirects an input/output request to the system components via an interconnect.

公开(公告)号：EP2021939A1

公开(公告)日：2009-02-11

申请号：EP07752703.4

申请日：2007-03-08

申请人： Microsoft Corporation

发明人： MICHAEL, Michael L. ,  SCHEIDEL, William L. ,  LEIS, Benjamin Alan ,  MEHRA, Karan ,  RAMAN, Venkatasubrahmanyam ,  VARAVA, Natalia V.

IPC分类号： G06F15/16

CPC分类号： G06F9/5066 ,  G06F9/4401 ,  G06F9/45533 ,  G06F2009/45575 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

摘要： Physical (or prior virtual) machine volumes can be converted to virtual machines at a virtual machine host while the physical machines are running. In one implementation, a volume shadow copy service can be used to create an application (and/or file system)-consistent snapshot of one or more physical machine volumes while the one or more volumes are running. The snapshot data can then be transferred to a mounted virtual hard disk file (dynamic or fixed) at a virtual machine host. Operational information (e.g., boot record, system registry, drivers, devices, configuration preferences, etc.) associated with the virtual hard disk file and the operating system(s) within the virtual machine can then be modified as appropriate to ensure that the corresponding virtual machine is bootable and functional at the virtual machine host. The virtual hard disk file can then be un-mounted, and used as a new virtual machine.

公开(公告)号：EP2742427B1

公开(公告)日：2018-03-07

申请号：EP12773387.1

申请日：2012-08-08

申请人： Consiglio Nazionale Delle Ricerche ,  Universita' Della Calabria

发明人： TALIA, Domenico ,  MASTROIANNI, Carlo ,  FORESTIERO, Agostino ,  PAPUZZO, Giuseppe ,  GIORDANELLI, Raffaele

IPC分类号： G06F9/50 ,  G06F9/455

CPC分类号： G06F9/5016 ,  G06F9/45533 ,  G06F9/5072 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

摘要： Assigning of application-hosting virtual machines to a plurality of servers inclusive of active and inactive servers in a data or calculation center is described.

公开(公告)号：EP2646909A1

公开(公告)日：2013-10-09

申请号：EP11790607.3

申请日：2011-11-28

申请人： Orange

发明人： LE SAUX, Louis-Marie ,  SAINO, Lorenzo ,  VENNEGUES, Elise

IPC分类号： G06F9/50 ,  G06F9/455 ,  G06F1/32

CPC分类号： G06F9/50 ,  G06F1/3203 ,  G06F1/3212 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/174 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

摘要： Method of operating a communication device offering a plurality of features (10) by means of a plurality of virtual machines (8) which run on a virtualized representation of a plurality of hardware components (6). The method comprises: obtaining a mapping (12,13,14,15) between at least some features of said plurality of features and corresponding sets of virtual machines of said plurality of virtual machines and hardware components of said plurality of hardware components which are required to enable said features; and upon deciding to activate or deactivate at least one group of features of said plurality of features, switching on or off virtual machines of said plurality of virtual machines and hardware components of said plurality of hardware components depending on said mapping.

公开(公告)号：EP2458501A1

公开(公告)日：2012-05-30

申请号：EP10306324.4

申请日：2010-11-30

申请人： France Telecom

发明人： Le Saux, Louis Marie ,  Saino, Lorenzo ,  Vennegues, Elise

IPC分类号： G06F9/50 ,  G06F9/455 ,  G06F1/32

CPC分类号： G06F9/50 ,  G06F1/3203 ,  G06F1/3212 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/174 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

摘要： Method of operating a communication device offering a plurality of features (10) by means of a plurality of virtual machines (8) which run on a virtualized representation of a plurality of hardware components (6). The method comprises: obtaining a mapping (12,13,14,15) between at least some features of said plurality of features and corresponding sets of virtual machines of said plurality of virtual machines and hardware components of said plurality of hardware components which are required to enable said features; and upon deciding to activate or deactivate at least one group of features of said plurality of features, switching on or off virtual machines of said plurality of virtual machines and hardware components of said plurality of hardware components depending on said mapping.

摘要翻译： 操作通过在多个硬件组件（6）的虚拟化表示上运行的多个虚拟机（8）来提供多个特征（10）的通信设备的方法。 所述方法包括：在所述多个特征的至少一些特征与所述多个虚拟机中的所述多个虚拟机的所述虚拟机的对应组和所述多个硬件组件的硬件组件之间获得需要的映射（12,13,14,15） 以实现所述特征; 并且在决定激活或去激活所述多个特征的至少一组特征时，根据所述映射来打开或关闭所述多个虚拟机的虚拟机和所述多个硬件组件的硬件组件。

公开(公告)号：EP2228727A3

公开(公告)日：2010-10-20

申请号：EP10167240.0

申请日：2004-07-12

申请人： MicroUnity Systems Engineering, Inc.

发明人： Hansen, Craig ,  Moussouris, John ,  Massalin, Alexia

IPC分类号： G06F12/00 ,  H03M13/41

CPC分类号： G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.

公开(公告)号：EP2226725A2

公开(公告)日：2010-09-08

申请号：EP10167233.5

申请日：2004-07-12

申请人： MicroUnity Systems Engineering, Inc.

发明人： Hansen, Craig ,  Massalin, Alexia ,  Moussouris, John

IPC分类号： G06F12/00

CPC分类号： G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.

摘要翻译： 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且通过使用通用寄存器的内容来显着地大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度可访问数量，则获得性能优点。

公开(公告)号：EP1652090A2

公开(公告)日：2006-05-03

申请号：EP04756853.0

申请日：2004-07-12

申请人： MicroUnity Systems Engineering, Inc.

发明人： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC分类号： G06F12/00

CPC分类号： G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.