摘要:
A solar power generation system (10) includes a control system (20) and a DC to AC converter (16) coupled to a photovoltaic (PV) module (14) and for supplying power to a power network (18). The control system includes a power point tracker (22) to extract either maximum power available from the PV module or less than maximum power available from the PV module, a frequency monitor (24) to obtain a network frequency from the power network, an internal reference frame element (26) to provide an internal reference frequency of the solar power generation system, a frequency comparator (28) to compare the network frequency and the internal reference frequency, and a command signal generator (30) to use the frequency comparison to determine whether a transient increase or decrease in commanded output power is warranted and to provide a command signal.
摘要:
A solar power generation system (10) includes a control system (20) and a DC to AC converter (16) coupled to a photovoltaic (PV) module (14) and for supplying power to a power network (18). The control system includes a power point tracker (22) to extract either maximum power available from the PV module or less than maximum power available from the PV module, a frequency monitor (24) to obtain a network frequency from the power network, an internal reference frame element (26) to provide an internal reference frequency of the solar power generation system, a frequency comparator (28) to compare the network frequency and the internal reference frequency, and a command signal generator (30) to use the frequency comparison to determine whether a transient increase or decrease in commanded output power is warranted and to provide a command signal.
摘要:
An AC to DC converter with harmonic suppression is provided. The harmonic suppression is provided by forcing an instantaneous current conflict between series connected rectifier bridges 54, 80, such that a voltage waveform at 6 times the AC supply frequency of the AC supply is automatically generated. This waveform is then injected via a injection circuit to give harmonic cancellation.
摘要:
A photovoltaic inverter having an inverter bridge section, a first output, a second output, and a power switch. The inverter bridge section is operable for converting DC electrical energy into AC electrical energy. The inverter bridge section has an output for outputting the AC electrical energy. The power switch is connected to the output of the inverter bridge section, the first output, and the second output. The power switch is selectively switchable between a first state in which the output of the inverter bridge section is connected to the first output via the power switch and a second state in which the output of the inverter bridge section is connected to the second output via the power switch.
摘要:
An electrical power system (10) for an aircraft includes an ac generator bus (16), an air conditioning system ('ACS') generator (42) and a main engine generator (46). The ACS generator (42) supplies primary ac power to the bus (16) while the frequency of the ac power is within a frequency range. If the frequency of the ac power goes outside the frequency range, the main engine generator (46) supplies backup ac power to the bus. The frequency of the ac power generated by the ACS generator (42) is maintained between upper and lower limits. Such ac power can be used directly by certain ac loads onboard the aircraft. Other ac loads onboard the aircraft are supplied with fixed frequency ac power by reduced-size inverters.
摘要:
An apparatus for controlling the output and torque of a synchronous alternator (15) has a controlled bridge rectifier (40) operable off synchronous for rectifying the alternating output and establishing a desired phase relationship between the alternating voltage and alternating current of the output winding (10). Phase locked loop control (80) may be employed for establishing and maintaining a desired phase relationship to control the output and torque.
摘要:
A linear feedback shift register comprises a shift register formed of first to (n)th flipflops cascaded in such a manner that an output of a (i)th flipflop is connected to an input of a (i+1)th flipflop, where 2≦n and 1≦i≦(n-1). First to (n)th output terminals are connected to outputs of the first to (n)th flipflops, respectively, and a clock terminal connected to a clock input of each of the flipflops. First to (n-1)th multiplexors of a "1-out-of-2" type are connected at their first input to a common preset value input terminal. Second inputs of the first to (n-1)th multiplexors are connected to the outputs of the first to (n-1)th flipflops, respectively. Each of the first to (n-1)th multiplexors has a control input connected to an individual control terminal. First to (n-1)th exclusive-OR gates are cascaded in such a manner that a first input of a (n-1)th exclusive-OR gate is connected to the output of the (n)th flipflop, a first input of an (i)th exclusive-OR gate is connected to an output of an (i+1)th exclusive-OR gate, and an output of the first exclusive-OR gate is connected to an input of the first flipflop. A second input of the (i)th exclusive-OR gate is connected to an output of the (i)th multiplexor. With this arrangement, a generator polynomial generated by the linear feedback shift register can be modified by controlling the multiplexors through the individual control terminals.
摘要:
A linear feedback shift register comprises a shift register formed of first to (n)th flipflops cascaded in such a manner that an output of a (i)th flipflop is connected to an input of a (i+1)th flipflop, where 2≦n and 1≦i≦(n-1). First to (n)th output terminals are connected to outputs of the first to (n)th flipflops, respectively, and a clock terminal connected to a clock input of each of the flipflops. First to (n-1)th multiplexors of a "1-out-of-2" type are connected at their first input to a common preset value input terminal. Second inputs of the first to (n-1)th multiplexors are connected to the outputs of the first to (n-1)th flipflops, respectively. Each of the first to (n-1)th multiplexors has a control input connected to an individual control terminal. First to (n-1)th exclusive-OR gates are cascaded in such a manner that a first input of a (n-1)th exclusive-OR gate is connected to the output of the (n)th flipflop, a first input of an (i)th exclusive-OR gate is connected to an output of an (i+1)th exclusive-OR gate, and an output of the first exclusive-OR gate is connected to an input of the first flipflop. A second input of the (i)th exclusive-OR gate is connected to an output of the (i)th multiplexor. With this arrangement, a generator polynomial generated by the linear feedback shift register can be modified by controlling the multiplexors through the individual control terminals.