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2039 条记录 (耗时 0.021 秒)

    NOISE FILTER
    1.
    发明公开
    NOISE FILTER 审中-公开

    公开(公告)号：EP4447317A1

    公开(公告)日：2024-10-16

    申请号：EP21967185.6

    申请日：2021-12-08

    申请人： MITSUBISHI ELECTRIC CORPORATION

    发明人： FURUSHO Yasuaki ,  KOBAYASHI Ryosuke ,  TERADA Minami ,  FUJITA Yuki

    IPC分类号： H03H11/04

    摘要： An object is to provide a noise filter that can achieve high reliability. A noise filter (10) includes: a noise detection unit (12) which detects a common mode noise (CN) flowing through an electric path (11); an amplification unit (16) which, on the basis of the common mode noise (CN) detected by the noise detection unit (12), generates a cancellation signal (CS) for canceling out the common mode noise (CN); an injection unit (14) which injects the cancellation signal (CS) into the electric path (11); an abnormality detection unit (17) which detects abnormality of the noise filter (10) on the basis of output voltage or output current of the cancellation signal (CS), and outputs an abnormality detection signal (AS); and a protection circuit (18) which inhibits an abnormal cancellation signal (CS) from being injected into the electric path (11), on the basis of the abnormality detection signal (AS).

    APPARATUS AND METHODS FOR LOCAL OSCILLATOR INTERFACE CIRCUITS WITH QUADRATURE CLOCK GENERATION AND PHASE CORRECTION
    3.
    发明公开
    APPARATUS AND METHODS FOR LOCAL OSCILLATOR INTERFACE CIRCUITS WITH QUADRATURE CLOCK GENERATION AND PHASE CORRECTION 审中-实审

    公开(公告)号：EP4422069A1

    公开(公告)日：2024-08-28

    申请号：EP24156447.5

    申请日：2024-02-07

    申请人： Analog Devices, Inc.

    发明人： XUESONG, Jiang

    IPC分类号： H03B5/12 ,  H03H11/22 ,  H03H7/20 ,  H03K5/15

    CPC分类号： H03B5/1237 ,  H03H11/22 ,  H03H7/20 ,  H03K5/15

    摘要： Apparatus and methods for oscillator interface circuits with quadrature clock generation and phase correction are disclosed. In certain embodiments, a clock system includes an external oscillator that provides a differential input clock signal, and a semiconductor die that includes a first pin that receives a non-inverted component of the differential input clock signal and a second pin that receives an inverted component of the differential input clock signal. The semiconductor die further includes an oscillator interface circuit that includes a first controllable resistor and a first controllable capacitor connected in series between the first pin and the second pin, and a second controllable resistor and a second controllable capacitor connected in series between the second pin and the first pin.

    CAPACITANCE MULTIPLIER FOR DECOUPLING CAPACITOR
    10.
    发明公开
    CAPACITANCE MULTIPLIER FOR DECOUPLING CAPACITOR 审中-公开

    公开(公告)号：EP4216435A1

    公开(公告)日：2023-07-26

    申请号：EP22215575.6

    申请日：2022-12-21

    申请人： Apple Inc.

    发明人： WOO, Sang Hyun

    IPC分类号： H03H11/48

    摘要： An integrated circuit may include one or more circuits coupled to capacitance multiplier circuitry. The capacitance multiplier circuitry may include a capacitor, fixed and tunable resistances, and a transconductance circuit. The tunable resistance can be adjusted to control the overall capacitance of the capacitance multiplier circuitry. The transconductance circuit may include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component may be a diode-connected transistor, a direct shorting wire, a resistor, an inductor, or a current source. The second electrical component may be a current source, a direct shorting wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuitry can provide a large adjustable amount of capacitance without a voltage drop and without consuming a large amount of power.