公开(公告)号：EP4143966A1

公开(公告)日：2023-03-08

申请号：EP21739538.3

申请日：2021-04-27

申请人： Robert Bosch Gesellschaft mit Beschränkter Haftung

发明人： RITTER, Rudolf

IPC分类号： H03F3/50 ,  H03K17/687 ,  H03K17/06

公开(公告)号：EP3859969A1

公开(公告)日：2021-08-04

申请号：EP21151446.8

申请日：2021-01-13

申请人： Analog Devices International Unlimited Company

发明人： MOBARAK, Mohamed ,  WEHEIBA, Mohamed ,  ESMAEL, Mohamed Moussa Ramadan

IPC分类号： H03F1/22 ,  H03F1/30 ,  H03F1/32 ,  H03F3/195 ,  H03F3/213 ,  H03F3/24 ,  H03F3/50

摘要： Bias arrangements for amplifiers are disclosed. An example bias arrangement for an amplifier includes a bias circuit, configured to produce a bias signal for the amplifier; a linearization circuit, configured to improve linearity of the amplifier by modifying the bias signal produced by the bias circuit to produce a modified bias signal to be provided to the amplifier; and a coupling circuit, configured to couple the bias circuit and the linearization circuit. Providing separate bias and linearization circuits coupled to one another by a coupling circuit allows separating a linearization operation from a biasing loop to overcome some drawbacks of prior art bias arrangements that utilize a single biasing loop.

公开(公告)号：EP3683963B1

公开(公告)日：2021-06-30

申请号：EP20151228.2

申请日：2020-01-10

发明人： BARBIERI, Mr. Andrea ,  VIDONI, Mr. Aldo

IPC分类号： H03F1/56 ,  H03F3/50 ,  H03F3/45 ,  H03H11/52

公开(公告)号：EP2937994B1

公开(公告)日：2020-10-28

申请号：EP15163426.8

申请日：2015-04-13

申请人： Analog Devices, Inc.

发明人： Ali, Ahmed M. A.

IPC分类号： H03F3/193 ,  H03F3/195 ,  H03F3/45 ,  H03F3/72 ,  H03K19/0175 ,  H03F1/32 ,  H03F3/50

公开(公告)号：EP3621198A1

公开(公告)日：2020-03-11

申请号：EP19193016.3

申请日：2019-08-22

申请人： Infineon Technologies AG

发明人： SCHRÖGENDORFER, Daniel

IPC分类号： H03F1/22 ,  H03F3/193 ,  H03F3/21 ,  H03F3/50

摘要： A multi-stage device (200-1) includes multiple stages such as a first stage (221-1) and a second stage (222-1). During operation, the first stage (221-1) receives an input signal and outputs an intermediate signal based on the input signal. The second stage (222-1) is coupled to the first stage to receive the intermediate signal and produce an output signal. According to one configuration, the second stage (222-1) includes a transistor (228) and a circuit path between the first stage (221-1) and the transistor (228). The transistor component (228) is controlled to derive the output signal from the intermediate signal inputted to the circuit path.

公开(公告)号：EP3350920A1

公开(公告)日：2018-07-25

申请号：EP16763849.3

申请日：2016-09-13

申请人： Firecomms Limited

发明人： MURPHY, Patrick ,  DONOVAN, Colm ,  CAHILL, Ciaran

IPC分类号： H03F3/345 ,  H03F3/08 ,  H03F3/50 ,  H03F1/22 ,  H03F1/32

摘要： A transconductance circuit has an input terminal (VIN) and an output terminal (Out), a first current source (4) having a gate connected to said input terminal (VIN); and a second current source (5), in parallel with said first current source, and having a higher transconductance and a wider dynamic range than the first current source. The current sources are configured so that at a low input voltage only the first current source (4) is on. A voltage drop circuit provides a lower bias voltage for the second current source than for the first current source.

公开(公告)号：EP3282581A1

公开(公告)日：2018-02-14

申请号：EP17184734.6

申请日：2017-08-03

申请人： MediaTek Inc.

发明人： TSAI, Chihhou

IPC分类号： H03F3/50 ,  H03F1/30

CPC分类号： G05F1/561 ,  G05F3/247 ,  H03F1/301 ,  H03F1/34 ,  H03F1/56 ,  H03F3/505 ,  H03F2200/18 ,  H03F2200/21 ,  H03F2200/288 ,  H03F2200/555 ,  H03F2200/69

摘要： A buffer stage includes a control circuit. The control circuit includes a voltage generator, a voltage-to-current converter, and a current-to-voltage converter. The voltage generator is configured to generate a compensation voltage. The voltage-to-current converter is configured to convert the compensation voltage into a compensation current. The current-to-voltage converter is configured to convert the compensation current into a recovery compensation voltage. The recovery compensation voltage is arranged for modifying an output voltage of the buffer stage.

摘要翻译： 缓冲级包括控制电路。 控制电路包括电压发生器，电压 - 电流转换器和电流 - 电压转换器。 电压发生器被配置为产生补偿电压。 电压 - 电流转换器被配置为将补偿电压转换为补偿电流。 电流至电压转换器被配置为将补偿电流转换为恢复补偿电压。 恢复补偿电压被布置用于修改缓冲级的输出电压。

公开(公告)号：EP3148073A1

公开(公告)日：2017-03-29

申请号：EP16170308.7

申请日：2016-05-19

申请人： MediaTek Inc.

发明人： WANG, Huai-Te

IPC分类号： H03F3/50

CPC分类号： H03F3/505 ,  H03F1/342 ,  H03F2200/129 ,  H03F2200/144 ,  H03F2200/21 ,  H03F2200/303 ,  H03F2200/42 ,  H03F2200/69 ,  H03F2203/45061 ,  H03F2203/45084 ,  H03F2203/5024

摘要： An apparatus (100) for performing capacitor amplification in an electronic device may include a first resistor (R cmp ) and a second resistor (R cmn ) that are connected in series and coupled between a set of input terminals of a receiver in the electronic device, a common mode capacitor (C cm ) having a first terminal coupled to a common mode terminal and having a second terminal, and an alternating current-coupled amplifier (110A), hereinafter AC-coupled amplifier, that is coupled between the common mode terminal and the second terminal of the common mode capacitor (C cm ). The first resistor (R cmp ) and the second resistor (R cmn ) may be arranged for obtaining a common mode voltage (V cm ) at the common mode terminal (V cm ) between the first resistor (R cmp ) and the second resistor (R cmn ). In addition, the common mode capacitor (C cm ) may be arranged for reducing a common mode return loss. Additionally, the AC-coupled amplifier (110A) may be arranged for performing capacitor amplification for the common mode capacitor (C cm ).

摘要翻译： 一种用于在电子设备中进行电容放大的设备（100）可以包括串联连接并连接在电子设备中的接收器的一组输入端之间的第一电阻器（R cmp）和第二电阻器（R cmn） ，具有耦合到共模端子并具有第二端子的第一端子的共模电容器（C cm）和耦合在共模端子之间的交流耦合放大器（110A），以下称为AC耦合放大器 和共模电容器的第二端子（C cm）。 可以布置第一电阻器（R cmp）和第二电阻器（R cmn），以获得第一电阻器（R cmp）和第二电阻器（R cmp）之间的共模端子（V cm）处的共模电压（V cm） R cmn）。 此外，可以设置共模电容器（C cm）以减少共模回波损耗。 此外，AC耦合放大器（110A）可以被布置为对共模电容器（C cm）进行电容放大。

公开(公告)号：EP3104523A1

公开(公告)日：2016-12-14

申请号：EP15191028.8

申请日：2015-10-22

申请人： MediaTek, Inc

发明人： SONG, Fei ,  SHANA'A, Osama K A ,  CHEE, YuenHui

IPC分类号： H03F3/50 ,  H03F3/195 ,  H03F3/30 ,  H03F3/45

摘要： A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

摘要翻译： 呈现低输出阻抗的宽带高线性缓冲电路包括第一PFET（PFET1），第二PFET（PFET2），第一NFET（NFET1）和第二NFET（NFET2）。 PFET1和PFET2的源极耦合到VDD。 PFET1的漏极耦合到输出引线。 PFET2作为电流源。 NFET1的漏极耦合到PFET2的漏极和PFET1的栅极。 NFET1的源极耦合到输出引线。 NFET2的源极耦合到地。 NFET2的漏极耦合到NFET1的源极和输出引线。 NFET1的栅极交流耦合到第一个输入引线。 在单端输入示例中，NFET2的栅极是交流耦合NFET1的漏极。 在差分输入示例中，NFET2的栅极被AC耦合到第二输入引线。 在另一个差分输入示例中，PFET2不仅仅是电流源，而是PFET2的栅极与第一个输入引线交流耦合。

公开(公告)号：EP2869465A1

公开(公告)日：2015-05-06

申请号：EP13191286.7

申请日：2013-11-01

申请人： NXP B.V.

发明人： Simin, Alexander ,  Gul, Hasan ,  Hoogzaad, Gian

IPC分类号： H03F3/191 ,  H03F1/22 ,  H03F3/50

CPC分类号： H03F1/26 ,  H03F1/22 ,  H03F1/226 ,  H03F3/191 ,  H03F3/193 ,  H03F3/50 ,  H03F2200/294 ,  H03F2200/451 ,  H04W88/08

摘要： A two-stage RF amplifier is provided. The first stage is a common-emitter transistor arrangement with a purely reactive degeneration impedance and an output impedance with a reactive component matched in frequency response to the degeneration impedance. The second stage is a buffer amplifier. The first amplifier can be designed for high gain which is flat over frequency by virtue of the reactive degeneration impedance. The first amplifier provides input matching, and the buffer provides output matching, with decoupling between the input and output.

摘要翻译： 提供两级RF放大器。 第一级是具有纯反应性退化阻抗的共发射极晶体管布置，以及具有与变性阻抗的频率响应匹配的无功分量的输出阻抗。 第二级是缓冲放大器。 第一放大器可以设计用于通过反应性退化阻抗在频率上平坦的高增益。 第一个放大器提供输入匹配，缓冲器提供输出匹配，输入和输出之间的去耦。