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2021 条记录 (耗时 0.021 秒)

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-实审

    公开(公告)号：EP4411818A1

    公开(公告)日：2024-08-07

    申请号：EP23205440.3

    申请日：2023-10-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： HEO, Jin ,  SONG, Jongkyu ,  KIM, Minho ,  SONG, Jooyoung ,  JEON, Chanhee

    IPC分类号： H01L27/02 ,  H03K19/003

    CPC分类号： H01L27/0266 ,  H01L27/0285 ,  H03K19/00315

    摘要： A semiconductor device (200) is provided. The semiconductor device (200) includes: a first power pad (201); a second power pad (202); a signal pad (203); a clamping circuit (230) connected between the first power pad (201) and the second power pad (202); a driving circuit (210) connected to the signal pad (203) and including a pull-up circuit and a pull-down circuit; and a first gate-off circuit (220) connected to the pull-down circuit. The first gate-off circuit (220) is configured to connect a gate of at least one pull-down element (PD) included in the pull-down circuit and a source of the at least one pull-down element (PD) to each other during an electrostatic discharge, ESD, event in which a high voltage is applied to the signal pad (203), and control a current generated by the high voltage to flow to the clamping circuit (230).

    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER
    4.
    发明公开
    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER 审中-实审

    公开(公告)号：EP4387102A1

    公开(公告)日：2024-06-19

    申请号：EP23198270.3

    申请日：2023-09-19

    申请人： GlobalFoundries U.S. Inc.

    发明人： Tran, Dzung T. ,  Pant, Deepti A. ,  Ahmed, Shibly S.

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00315

    摘要： Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.

    CIRCUITS FOR INVERTERS AND PULL-UP/PULL-DOWN CIRCUITS
    9.
    发明公开
    CIRCUITS FOR INVERTERS AND PULL-UP/PULL-DOWN CIRCUITS 审中-公开

    公开(公告)号：EP4224712A1

    公开(公告)日：2023-08-09

    申请号：EP22305133.5

    申请日：2022-02-08

    申请人： NXP USA, Inc.

    发明人： ABOUDA, Pascal Kamel ,  GUENDOUZ, Badr ,  MEDIOUNI, Hiba

    IPC分类号： H03K17/16 ,  H03K19/003

    摘要： A circuit is disclosed, comprising: an inverter comprising first and second inverter transistors, each having: a gate terminal connected in common to a drive node, a source terminal, connected to respective first and second voltage rails, and a drain terminal connected to a common first resistor, wherein an inverter output node is connected between the first resistor and the drain terminal of a shorting one of the transistors; a tying transistor connected between the drive node and the voltage rails to which the shorting transistor is connected; a biassing circuit connected to the tying transistor's control terminal and configured to be controlled by a local drive signal and bias the tying transistor control terminal to a voltage such that the tying transistor ties the drive node of the relevant voltage rail in response to the drive signal having a first state; and a circuit for providing the local drive signal.

    CHARGE INJECTION PROTECTION DEVICES AND METHODS FOR INPUT/OUTPUT INTERFACES
    10.
    发明公开
    CHARGE INJECTION PROTECTION DEVICES AND METHODS FOR INPUT/OUTPUT INTERFACES 审中-公开

    公开(公告)号：EP4213385A1

    公开(公告)日：2023-07-19

    申请号：EP23150543.9

    申请日：2023-01-06

    申请人： NXP B.V.

    发明人： Jain, Ashutosh ,  Mai, Khoi

    IPC分类号： H03K17/0812 ,  H03K19/003 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0185

    摘要： A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.