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1.发明公开
公开(公告)号：EP4471415A1
公开(公告)日：2024-12-04
申请号：EP23176647.8
申请日：2023-06-01
Applicant: Digital Gas Measurement Aps
Inventor： Popowicz, Grzegorz , Krzysztof, Adamski
Abstract: The invention relates to an electronic device configured for conversion of a digital signal received from at least one gas sensor containing digital signal processing, into an analog signal that is compatible with devices that were designed to work with sensors based on electro-galvanic fuel cell principle.
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公开(公告)号：EP3355819B1
公开(公告)日：2024-11-13
申请号：EP16787583.0
申请日：2016-09-26
Inventor： WIENER, Eitan T. , YATES, David C.
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3.发明公开
公开(公告)号：EP4390781A1
公开(公告)日：2024-06-26
申请号：EP23218412.7
申请日：2023-12-20
Inventor： JADOT, Baptiste , BILLIOT, Gérard , THONNART, Yvain
IPC: G06N10/40 , H03M1/66 , G11C27/02 , H01L29/423
CPC classification number: G06N10/40 , G11C27/024 , H01L29/423 , G06N10/00 , G06N3/065
Abstract: Ce circuit (100), relié au circuit quantique par des lignes de polarisation (11, 12, 13, 14), comporte : un convertisseur numérique analogique - DAC (102) délivrant une tension analogique (Ve) ; des cellules mémoires (110, 120, 130, 140), connectées en parallèle en sortie du DAC, chaque cellule mémoire comportant un interrupteur (I1, I2, I3, I4) et une capacité (C1, C2, C3, C4), la capacité mémorisant un niveau de potentiel auquel maintenir une ligne de polarisation connectée en sortie de la cellule mémoire ; et, un moyen de génération de signaux de commande (104) générant, en synchronisation avec le DAC, un signal de commande pour chaque interrupteur de chaque cellule mémoire, le signal de commande, une valeur de la capacité d'une cellule mémoire étant sélectionnée pour rendre négligeable une capacité parasite affectant la ligne de polarisation reliée à ladite cellule mémoire et qui circule parallèlement à une ligne de polarisation voisine.
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公开(公告)号：EP4377851A1
公开(公告)日：2024-06-05
申请号：EP22751797.6
申请日：2022-07-29
Applicant: Universal Quantum Ltd
Inventor： HUNTER, Iain Mcintosh
CPC classification number: G06N10/40 , H03M1/662 , B82Y10/00 , G11C27/024
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公开(公告)号：EP3997791B1
公开(公告)日：2024-04-17
申请号：EP20753481.9
申请日：2020-06-11
CPC classification number: H03M1/662 , H03M1/0678 , H03M1/0836 , H03M1/0624
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Patent Agency Ranking6.发明公开
公开(公告)号：EP4312376A1
公开(公告)日：2024-01-31
申请号：EP22187587.5
申请日：2022-07-28
Applicant: NXP B.V.
Inventor： Bajoria, Shagun , Bolatkale, Muhammed , Breems, Lucien Johannes , Rutten, Robert , Abo Alainein, Mohammed
Abstract: A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.
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公开(公告)号：EP4307566A1
公开(公告)日：2024-01-17
申请号：EP23182333.7
申请日：2023-06-29
Applicant: NXP USA, Inc.
Inventor： Abhishek, Kumar , Jin, Xiankun , Lehmann, Mark
Abstract: Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2 N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.
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公开(公告)号：EP4244982A1
公开(公告)日：2023-09-20
申请号：EP21805675.2
申请日：2021-11-10
Applicant: Stem Technologies/Ixora Holding B.V.
Inventor： VAN HANXLEDEN HOUWERT, Vincent Daniël
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公开(公告)号：EP4213393A1
公开(公告)日：2023-07-19
申请号：EP23151811.9
申请日：2023-01-16
Applicant: NXP B.V.
Inventor： OLIEMAN, Erik , VERLINDEN, René , KRANABENTER, Helmut
Abstract: A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO- signals, and outputs a second controlled LO signal output to a sense circuit.
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