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公开(公告)号：EP4120571A1
公开(公告)日：2023-01-18
申请号：EP21186151.3
申请日：2021-07-16
Applicant: NXP B.V.
Inventor： Bolatkale, Muhammed
Abstract: There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0'), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.
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2.发明公开
公开(公告)号：EP4109762A1
公开(公告)日：2022-12-28
申请号：EP22175844.4
申请日：2022-05-27
Applicant: NXP B.V.
Inventor： Rutten, Robert , van der Ploeg, Hendrik , Breems, Lucien Johannes , Kessel, Martin , Bolatkale, Muhammed , Burdiek, Bernhard , Zupke, Manfred , Brekelmans, Johannes Hubertus Antonius , Bajoria, Shagun
Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.
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公开(公告)号：EP4329201A1
公开(公告)日：2024-02-28
申请号：EP23185554.5
申请日：2023-07-14
Applicant: NXP B.V.
Inventor： Breems, Lucien Johannes , Bolatkale, Muhammed
IPC: H03M3/00
Abstract: A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.
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4.发明公开
公开(公告)号：EP4312376A1
公开(公告)日：2024-01-31
申请号：EP22187587.5
申请日：2022-07-28
Applicant: NXP B.V.
Inventor： Bajoria, Shagun , Bolatkale, Muhammed , Breems, Lucien Johannes , Rutten, Robert , Abo Alainein, Mohammed
Abstract: A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.
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公开(公告)号：EP4125221A1
公开(公告)日：2023-02-01
申请号：EP22185228.8
申请日：2022-07-15
Applicant: NXP B.V.
Inventor： Rutten, Robert , Kessel, Martin , van der Ploeg, Hendrik , Breems, Lucien Johannes , Bolatkale, Muhammed , Pol, Evert-Jan , Zupke, Manfred , Burdiek, Bernard , Brekelmans, Johannes Hubertus Antonius , Bajoria, Shagun
IPC: H03M3/02
Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
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Patent Agency Ranking6.发明公开
公开(公告)号：EP4033671A1
公开(公告)日：2022-07-27
申请号：EP21211249.4
申请日：2021-11-30
Applicant: NXP B.V.
Inventor： Zhang, Chenming , Breems, Lucien Johannes , Bolatkale, Muhammed
IPC: H03M3/00
Abstract: The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.
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公开(公告)号：EP4274099A1
公开(公告)日：2023-11-08
申请号：EP22171861.2
申请日：2022-05-05
Applicant: NXP B.V.
Inventor： Bolatkale, Muhammed , Breems, Lucien Johannes , Cenci, Pierluigi , Bajoria, Shagun , Abo Alainein, Mohammed
Abstract: There is described an analog-to-digital converter, ADC, device (100), comprising:
i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13);
ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and
iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to:
swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).-
公开(公告)号：EP3340475A1
公开(公告)日：2018-06-27
申请号：EP16206388.7
申请日：2016-12-22
Applicant: NXP B.V.
Inventor： Breems, Lucien Johannes , Bolatkale, Muhammed
CPC classification number: H03M3/352 , H03M1/0863 , H03M1/12 , H03M3/344 , H03M3/376 , H03M3/412 , H03M3/458 , H03M3/464
Abstract: The disclosure relates to a data processor comprising: a data processing module comprising: an input for receiving an input signal; an output for providing a quantized output signal; a combining unit configured to combine a feedback signal from the output with the input signal; and a quantizer configured to provide the quantized output signal based on the combined signal, wherein the quantized output signal comprises a metastability error, and a correction module configured to: receive the quantized output signal; generate a full-scale digital signal based on the quantized output signal; determine the a metastability error in the full-scale digital quantized output signal; and provide a compensated output signal based on the quantized output signal and the determined metastability error.
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公开(公告)号：EP3240197A1
公开(公告)日：2017-11-01
申请号：EP16167566.5
申请日：2016-04-28
Applicant: NXP B.V.
Inventor： Bolatkale, Muhammed , Breems, Lucien Johannes
CPC classification number: H04L25/08 , H03M1/001 , H03M1/1009 , H04B1/0007 , H04B1/109 , H04B1/123
Abstract: A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.
Abstract translation: 一种接收器电路，包括：输入端，被配置为接收输入信号; 前馈ADC，被配置为基于输入信号提供前馈数字信号; 前馈DAC，被配置为基于前馈数字信号提供前馈模拟信号; 前馈减法器，被配置为基于前馈模拟信号和输入信号之间的差值提供误差信号; 误差LNA，被配置为基于误差信号提供放大的误差信号; 误差ADC，被配置为基于放大的误差信号提供数字放大的误差信号; 混频器，被配置为对输入端和误差ADC之间的信号路径中的信号进行下变频; 以及错误消除块，被配置为基于数字放大错误信号和前馈数字信号之间的差提供错误消除信号。
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公开(公告)号：EP3174210A1
公开(公告)日：2017-05-31
申请号：EP15196076.2
申请日：2015-11-24
Applicant: NXP B.V.
Inventor： Niehof, Jan , Bajoria, Shagun , Bolatkale, Muhammed , Rutten, Robert , Breems, Lucien Johannes , Brekelmans, Johannes Hubertus Antonius
CPC classification number: H04W74/002 , H03M1/0678 , H03M1/08 , H03M1/123 , H03M1/183 , H04L5/0051
Abstract: A processor comprising: a first-receiver-node for receiving a first-receiver-signal; a second-receiver-node for receiving a second-receiver-signal; a first-output-node for coupling to a digital-baseband-processor; a second-output-node for coupling to the digital-baseband-processor; a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe comprises: a first-analogue-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node; and a first-ADC-output coupled to the first-output-node; wherein the first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node; and a configurable-data-pipe extending between the second-receiver-node and the second-output-node. The configurable-data-pipe comprises: a configurable-pipeline-multiplexer comprising: a first-MUX-input-node coupled to the second-receiver-node; a second-MUX-input-node coupled to the first-reference-node; and a MUX-output-node. The configurable-data-pipe also comprises a second-analogue-to-digital-converter comprising: a second-ADC-input coupled to the MUX-output-node; and a second-ADC-output coupled to the second-output-node. When the configurable-pipeline-multiplexer is configured to couple the second-MUX-input-node to the MUX-output-node, the second-analogue-to-digital-converter is configured to provide a first-digital-reference-signal to the second-output-node.
Abstract translation: 一种处理器，包括：用于接收第一接收机信号的第一接收机节点; 第二接收机节点，用于接收第二接收机信号; 用于耦合到数字基带处理器的第一输出节点; 用于耦合到数字基带处理器的第二输出节点; 在第一接收器节点和第一输出节点之间延伸的第一有效数据管道。 第一有源数据管包括：第一模数转换器，其包括耦合到第一接收机节点的第一ADC输入; 以及耦合到第一输出节点的第一ADC输出; 其中所述第一模拟至数字转换器经配置以将第一数字信号提供到所述第一输出节点。 处理器包括第一参考节点; 以及在第二接收器节点和第二输出节点之间延伸的可配置数据管道。 该可配置数据管道包括：可配置流水线多路复用器，包括：耦合到第二接收机节点的第一MUX输入节点; 耦合到第一参考节点的第二MUX输入节点; 和一个MUX输出节点。 该可配置数据管道还包括第二模数转换器，该第二模数转换器包括：耦合到该MUX输出节点的第二ADC输入; 以及耦合到第二输出节点的第二ADC输出。 当可配置流水线多路复用器被配置为将第二MUX输入节点耦合到MUX输出节点时，第二模拟到数字转换器被配置为将第一数字参考信号提供给 第二个输出节点。
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