公开(公告)号：JP2005167057A

公开(公告)日：2005-06-23

申请号：JP2003405622

申请日：2003-12-04

Applicant: Semiconductor Energy Lab Co Ltd ,  Sharp Corp ,  シャープ株式会社 ,  株式会社半導体エネルギー研究所

Inventor： ASANO ETSUKO ,  ARAO TATSUYA ,  MATSUO TAKUYA ,  KIYOUHO MASANORI ,  KITAKADO HIDETO

IPC: H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To avoid hot carrier deterioration in a thin film transistor having an LDD structure or a GOLD structure.
SOLUTION: Doping to an LDD is made slightly high dose/high acceleration. An upper side layer which is subjected to doping of relatively low concentration and a lower side layer which is subjected to doping of relatively high concentration are formed for avoiding hot carrier deterioration and also avoiding an increase of ON resistance.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了避免具有LDD结构或GOLD结构的薄膜晶体管的热载流子劣化。

解决方案：对LDD的掺杂量略高，剂量/高加速度。 形成经受相对低浓度掺杂的上侧层和经受相对高浓度掺杂的下侧层，以避免热载流子劣化，并且还避免了导通电阻的增加。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005123360A

公开(公告)日：2005-05-12

申请号：JP2003355882

申请日：2003-10-16

Applicant: Semiconductor Energy Lab Co Ltd ,  Sharp Corp ,  シャープ株式会社 ,  株式会社半導体エネルギー研究所

Inventor： ARAO TATSUYA ,  NODA GOJI ,  MATSUO TAKUYA ,  KITAKADO HIDETO ,  KIYOUHO MASANORI

IPC: G02F1/1343 ,  G02F1/1368 ,  H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/77 ,  H01L21/86 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/78621 ,  H01L27/1214 ,  H01L29/6675 ,  H01L29/78648

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can be reduced in manufacturing cost by reducing the number of masks, and also to provide its manufacturing method. SOLUTION: In manufacturing the semiconductor device, a semiconductor layer 3 including a source and a drain regions 10 and 11 and LDD regions 16 and 17, a gate insulation film 5, and a gate electrode 6 are formed, and a first and a second interlayer insulation films 24 and 25 are formed thereon. In the interlayer insulation films, contact holes 25a and 25c which are positioned above the source and drain regions respectively and an opening 25b which is positioned above the gate electrode and the LDD regions are formed. Within the opening, a second gate electrode 26b consisting of a transparent conductive film is so formed as to cover the gate electrode and the LDD regions, and a pixel electrode 26a is formed on the second interlayer insulation film. Then, the gate insulation film inside the contact holes is removed, and interconnections 27 and 28 connected to the source and drain regions respectively are formed. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供通过减少掩模的数量可以降低制造成本的半导体器件，并且还提供其制造方法。 解决方案：在制造半导体器件时，形成包括源极和漏极区域10和11以及LDD区域16和17的半导体层3，栅极绝缘膜5和栅极电极6，并且第一和 在其上形成第二层间绝缘膜24和25。 在层间绝缘膜中，分别形成位于源极和漏极区之上的接触孔25a和25c以及位于栅电极和LDD区之上的开口25b。 在开口内，由透明导电膜构成的第二栅电极26b形成为覆盖栅电极和LDD区，并且在第二层间绝缘膜上形成像素电极26a。 然后，去除接触孔内部的栅极绝缘膜，并分别连接到源区和漏极区的互连27和28。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2008256854A

公开(公告)日：2008-10-23

申请号：JP2007097569

申请日：2007-04-03

Applicant: Sharp Corp ,  シャープ株式会社

Inventor： TAKAHASHI DAISUKE ,  KIYOUHO MASANORI ,  OKAMOTO MASAYA

IPC: G02F1/1368 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To reduce crosstalk between respective wires in a TFT array substrate. SOLUTION: The TFT array substrate is arranged on a transparent substrate, and is equipped with: a gate wire 1 which is branched from a gate electrode 4a and is extended; a semiconductor layer 3 covering the upper portion of the gate electrode 4a across a lower insulating film; source/drain electrodes 4b, 4c arranged on the upper side of the gate electrode 4a, while being independent of each other, in such a way that a portion of each of them overlaps the gate electrode 4a while not intersecting the gate wire 1 across the semiconductor layer 3; an upper insulating film covering the source/drain electrodes 4b, 4c; an upper source wire 8 arranged on the upper side of the upper insulating film in a direction intersecting the gate wire 1 and connected with the source electrode 4b; and a transparent pixel electrode 11 electrically connected to the drain electrode 4c, wherein the upper insulating film is arranged between the gate wire 1 and the upper source wire 8 at least on an intersection 21 where the gate wire 1 and the upper source wire 8 intersect each other. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了减少TFT阵列基板中各导线之间的串扰。 解决方案：TFT阵列基板设置在透明基板上，并且配备有从栅电极4a分支并延伸的栅极线1; 覆盖栅电极4a的上部的半导体层3穿过下绝缘膜; 源极/漏极电极4b，4c，其彼此独立地设置在栅电极4a的上侧，使得它们中的每一个与栅极电极4a重叠，同时不与栅极线1相交 半导体层3; 覆盖源/漏电极4b，4c的上绝缘膜; 与源极电极4b连接的与栅极配线1相交的方向配置在上绝缘膜的上侧的上部源线8; 以及电连接到漏电极4c的透明像素电极11，其中，上绝缘膜至少在栅极线1和上源极线8相交的交叉点21上布置在栅极线1和上源极线8之间 彼此。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008210967A

公开(公告)日：2008-09-11

申请号：JP2007045701

申请日：2007-02-26

Applicant: Sharp Corp ,  シャープ株式会社

Inventor： KIYOUHO MASANORI ,  TAKAHASHI DAISUKE ,  OKAMOTO MASAYA

IPC: H01L21/3205 ,  G02B5/20 ,  G02F1/1343 ,  G09F9/00 ,  H01L21/288 ,  H01L51/50 ,  H05B33/10

Abstract: PROBLEM TO BE SOLVED: To provide a forming method of a pattern capable of forming a pattern having excellent pattern precision by a simple process.
SOLUTION: The pattern forming method allows a pattern to be formed on a substrate 10 via an insulating layers 11. The method includes: a process for arranging the insulating layer 11 on the surface of the substrate 10; a process for forming a liquid-repellent layer 12 having repellency to a pattern forming material 15 of liquid for forming the pattern onto the surface of the insulating layer 11; a process for forming a recess 14 corresponding to the pattern at a region where the liquid-repellent layer 12 is formed on the surface of the insulating layer 11; a process for arranging the pattern forming material 15 at the recess 14; and a process for baking the pattern forming material 15.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供通过简单的工艺能够形成具有优异图案精度的图案的图案的形成方法。 解决方案：图案形成方法允许通过绝缘层11在衬底10上形成图案。该方法包括：将绝缘层11布置在衬底10的表面上的工艺; 用于形成对形成图案的液体的图案形成材料15具有排斥性的防液层12的工艺，形成在绝缘层11的表面上; 在绝缘层11的表面形成有疏液层12的区域形成与图案相对应的凹部14的工序; 用于将图案形成材料15布置在凹部14处的工艺; 以及烘烤图案形成材料15的方法。（C）2008，JPO＆INPIT

公开(公告)号：JP2008209732A

公开(公告)日：2008-09-11

申请号：JP2007047162

申请日：2007-02-27

Applicant: Sharp Corp ,  シャープ株式会社

Inventor： KIYOUHO MASANORI ,  TAKAHASHI DAISUKE ,  OKAMOTO MASAYA

IPC: G09F9/30 ,  G02F1/1343

Abstract: PROBLEM TO BE SOLVED: To enhance a numerical aperture without increasing a risk of leakage and crosstalk between wirings in a thin-film transistor (TFT) array substrate.
SOLUTION: The TFT substrate is equipped with: a transparent substrate 50; gate wirings 1 and Cs common wirings 12 arranged on the transparent substrate 50; source electrodes 4b and drain electrodes 4c which are respectively and separately arranged so as to partially superimpose the upper sides of gate electrodes 4a via a semiconductor layer 3; an upper insulation film 6 which covers them; source wirings 8 arranged in the direction intersecting the gate wirings 1; Cs wirings 10 which superimpose the Cs common wirings 12; transparent pixel electrodes 11 electrically connected with the Cs lines 10; and drain-sub capacitance line wiring 10a which electrically connect the drain electrodes 4c with the Cs lines 10. The drain-sub capacitance line wiring 10a partially superimpose the source wirings 8 via the upper insulation film 6.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了增加数值孔径，而不增加薄膜晶体管（TFT）阵列基板中的布线之间的泄漏和串扰的风险。 TFT基板配备有：透明基板50; 布置在透明基板50上的栅极布线1和Cs公共布线12; 源电极4b和漏极电极4c，其分别并且分别布置成经由半导体层3部分地叠加栅极电极4a的上侧; 覆盖它们的上绝缘膜6; 沿着与栅极配线1交叉的方向排列的源极布线8; Cs布线10，其叠加Cs公共布线12; 与Cs线10电连接的透明像素电极11; 以及将漏极电极4c与Cs线10电连接的漏极 - 次级电容配线10a。漏极 - 次级电容配线10a经由上部绝缘膜6部分地叠加源极配线8.权利要求（C） 2008年，日本特许厅和INPIT

公开(公告)号：JP2005116729A

公开(公告)日：2005-04-28

申请号：JP2003347935

申请日：2003-10-07

Applicant: Sharp Corp ,  シャープ株式会社

Inventor： KIYOUHO MASANORI ,  TOYOSHIMA TETSURO

IPC: B23K26/00 ,  H01L21/20 ,  H01L21/268

Abstract: PROBLEM TO BE SOLVED: To provide a laser annealing device capable of keeping the average energy density of laser light with which a workpiece is irradiated constant even when a profile of the laser light is changed. SOLUTION: In the laser annealing device 10 when an irradiation optical system unit 12 irradiates laser light emitted from a laser oscillator unit 11 to an irradiation position of a substrate 17, a Joule meter 13 detects laser light energy, and a profile meter 14 detects the profile of the laser light. On the basis of these detection outputs, calculation means 15 calculates the average energy density of the laser light irradiated to the substrate 17, and control means 16 controls the average energy density of the laser light with which the substrate 17 is irradiated such that it becomes a predetermined constant value in response to an output of the calculation means 15. With the control, the average energy density of the laser light with which the substrate 17 is irradiated is kept unchanged. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种即使当激光的轮廓改变时，能够保持工件被照射的激光的平均能量密度恒定的激光退火装置。 解决方案：在激光退火装置10中，当照射光学系统单元12将从激光振荡器单元11发射的激光照射到基板17的照射位置时，焦耳仪13检测激光能量，并且轮廓仪 14检测激光的轮廓。 在这些检测输出的基础上，计算单元15计算照射到基板17的激光的平均能量密度，控制单元16控制照射基板17的激光的平均能量密度， 响应于计算装置15的输出而具有预定的恒定值。通过该控制，基板17被照射的激光的平均能量密度保持不变。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000076625A

公开(公告)日：2000-03-14

申请号：JP24230298

申请日：1998-08-27

Applicant: Sharp Corp ,  シャープ株式会社

Inventor： DEGUCHI HARUHIKO ,  KOMODA TOMOHISA ,  MICHIJIMA MASASHI ,  NAKABAYASHI KEIYA ,  ISONO HITOSHI ,  KIYOUHO MASANORI

IPC: G11B5/39

Abstract: PROBLEM TO BE SOLVED: To obtain a magnetoresistive effect element capable of making a desired size for the area in which magnetization rotates in accordance with an external magnetic field, and to obtain a manufacturing method of the element.
SOLUTION: The magnetoresistive effect element is equipped with a magnetic domain control layer 3, 3 in such a manner as to come into contact with the end area E, E of a spin valve film 2. In addition, an electrode layer 4, 4 is arranged so as to cover the end area E, E of the spin valve film 2. The magnetoresistive effect is measured for the center area C where the magnetization of a free magnetizing layer 12 is unfixed by the magnetic domain control layer 3; therefore, regardless of the size of the control power of the magnetic domain control layer 3, the magnetoresistive effect can be measured constantly from the prescribed area (center area C).
COPYRIGHT: (C)2000,JPO

Abstract translation: 要解决的问题：为了获得能够根据外部磁场使磁化旋转的区域产生所需尺寸的磁阻效应元件，并获得元件的制造方法。 解决方案：磁阻效应元件以与自旋阀膜2的端部区域E，E接触的方式配备有磁畴控制层3,3。另外，电极层4,4是 被布置成覆盖自旋阀膜2的端部区域E，E。测量自由磁化层12的磁化被磁畴控制层3固定的中心区域C的磁阻效应; 因此，无论磁畴控制层3的控制功率的大小如何，都可以从规定的区域（中心区域C）恒定地测量磁阻效果。