Semiconductor wafer alignment apparatus

    公开(公告)号:JP5324232B2

    公开(公告)日:2013-10-23

    申请号:JP2009002312

    申请日:2009-01-08

    CPC classification number: H01L21/681

    Abstract: A wafer has an annular ridge formed along an outer periphery thereof to serve as a reinforcing portion, and a circuit pattern surrounded with the reinforcing portion. The wafer is placed on a wafer placement plane of a holding stage in a state that the circuit pattern is directed downward. The wafer placement plane is larger in size than the wafer. On the holding stage, a center of the wafer is aligned with a center of the holding stage in such a manner that a plurality of guide pins are engaged with relevant cutout portions formed on the reinforcing portion. Then, the holding stage rotates while suction-holding the reinforcing portion of the wafer, and simultaneously a photosensor detects a portion for alignment formed on the outer periphery of the wafer.

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