公开(公告)号：JP2013008973A

公开(公告)日：2013-01-10

申请号：JP2012140830

申请日：2012-06-22

Applicant: Samsung Electro-Mechanics Co Ltd ,  サムソン エレクトロ−メカニックス カンパニーリミテッド.

Inventor： AHN YON-GYU ,  YI BYON-HWA ,  PARK MN-CHOL ,  SONG YONG-HUN ,  YI MI-HEE

IPC: H01G4/232 ,  H01G4/30

CPC classification number: H01G4/01 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: PROBLEM TO BE SOLVED: To provide a chip type multilayer capacitor that can achieve size reduction and higher capacity while reducing a vibration sound caused between internal electrodes when power supply is applied.SOLUTION: A chip type multilayer capacitor according to an embodiment of the present invention comprises: a ceramic main body including a dielectric layer formed with a thickness of 3 μm or less, which is greater than or equal to 10 times of the average diameter of a grain; first and second external electrodes formed at both end faces of the ceramic main body in the length direction; first and second band parts having different lengths from each other, and extending from the first and second external electrodes on an L-W plane inside the ceramic main body in the length direction; and third and fourth band parts having different lengths from each other, and extending from the first and second external electrodes on an L-T plane inside the ceramic main body in the length direction.

Abstract translation: 要解决的问题：提供一种能够实现尺寸减小和更高容量的芯片型多层电容器，同时在施加电源时减少在内部电极之间产生的振动声音。 解决方案：根据本发明实施例的芯片型层叠电容器包括：陶瓷主体，其包括形成为厚度为3μm以下的电介质层，其大于或等于平均值​​的10倍 谷物直径; 第一和第二外部电极，其形成在陶瓷主体的长度方向的两端面; 第一和第二带部分具有彼此不同的长度，并且在第一和第二外部电极沿着长度方向在陶瓷主体内的L-W平面上延伸; 以及具有彼此不同长度的第三和第四带状部分，并且在长度方向上从陶瓷主体内部的L-T平面上的第一外部电极和第二外部电极延伸。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013008972A

公开(公告)日：2013-01-10

申请号：JP2012140668

申请日：2012-06-22

Applicant: Samsung Electro-Mechanics Co Ltd ,  サムソン エレクトロ−メカニックス カンパニーリミテッド.

Inventor： AHN YON-GYU ,  YI BYON-HWA ,  PARK MN-CHOL ,  SONG YONG-HUN ,  YI MI-HEE

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/232

CPC classification number: H01G4/1272 ,  H01G2/065 ,  H01G4/005 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30

Abstract: PROBLEM TO BE SOLVED: To provide a chip type multilayer capacitor that achieves size reduction and higher capacity while reducing acoustic noise.SOLUTION: A chip type multilayer capacitor according to an embodiment of the present invention comprises: a ceramic main body including a stack of dielectric layers each formed with a thickness of 3 μm or less, which is greater than or equal to 10 times of the average size of a grain; first and second external electrodes having different polarities from each other and formed at both ends of the ceramic main body in the length direction; a first internal electrode having one end forming a first margin with one end face of the ceramic main body to be provided with the second external electrode, and the other end being extracted by the first external electrode; and a second internal electrode having one end forming a second margin with the other end face of the ceramic main body to be provided with the first external electrode, and the other end being extracted by the second external electrode. The first margin and the second margin have different widths under a condition within 200 μm.

Abstract translation: 要解决的问题：提供一种在减小声学噪声的同时实现尺寸减小和更高容量的芯片型多层电容器。 解决方案：根据本发明实施例的芯片型层叠电容器包括：陶瓷主体，其包括各自形成为厚度为3μm以下的电介质层，其大于或等于10倍 的平均粒度; 第一外部电极和第二外部电极彼此具有不同的极性并形成在陶瓷主体的长度方向的两端; 第一内部电极，其一端形成具有陶瓷主体的一个端面的第一边缘，以设置第二外部电极，另一端由第一外部电极提取; 以及第二内部电极，其一端与陶瓷主体的另一端面形成第二边缘，以设置第一外部电极，另一端由第二外部电极提取。 第一边缘和第二边缘在200μm以内的条件下具有不同的宽度。 版权所有（C）2013，JPO＆INPIT