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公开(公告)号：JP2008304464A
公开(公告)日：2008-12-18
申请号：JP2008150970
申请日：2008-06-09
Applicant: Tektronix Inc , テクトロニクス・インコーポレイテッドTektronix,Inc.
Inventor： TRAN QUE THUY , KELLY DAVID L , HITE DAVID G , SMITH PATRICK A , LENIHAN THOMAS F
IPC: G01R13/20
CPC classification number: G01R13/0254 , G01R13/029
Abstract: PROBLEM TO BE SOLVED: To provide a serial trigger circuit which does not need an expensive precision high-power circuit, design accuracy, high costs, and complicated software.
SOLUTION: The position lock trigger apparatus employs oscilloscope circuitry and accompanying control software to provide to a user a capability to trigger an oscilloscope on a selected bit position in a received serial bit stream having a fixed pattern length, using either a synchronized, recovered, or external clock source. The selected trigger position can be moved forward or backward along the serial bit stream by one or more serial bit positions at a time in order to examine the entirety of the fixed pattern length serial bit stream, with or without regard to actual bit sequences occurring in the serial stream.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：提供不需要昂贵的高精度大功率电路的串行触发电路，设计精度高，成本高，而且复杂的软件。 位置锁定触发装置使用示波器电路和伴随的控制软件向用户提供在具有固定模式长度的接收串行比特流中的所选位位置上触发示波器的能力，使用同步的， 恢复或外部时钟源。 所选择的触发位置可以沿着串行比特流一次一个或多个串行比特位置向前或向后移动，以便检查固定模式长度串行比特流的整体，无论是否与实际的比特序列出现在 串行流。 版权所有（C）2009，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：JP2012154932A
公开(公告)日：2012-08-16
申请号：JP2012015155
申请日：2012-01-27
Applicant: Tektronix Inc , テクトロニクス・インコーポレイテッドTektronix,Inc.
Inventor： SMITH PATRICK A , KNIERIM DANIEL G , CALVIN JOHN C , HAZZARD SHANE A
CPC classification number: G01R13/0254 , G01R23/02 , G01R31/31727 , H03L7/093
Abstract: PROBLEM TO BE SOLVED: To instantaneously trigger on a frequency deviation dF/dT of an SSC signal.SOLUTION: A signal received at an input terminal 210 of a test and measurement instrument 200 is low-pass filtered and transmitted to dF/dT trigger circuitry 220. The dF/dT trigger circuitry 220 includes trigger circuitry and a PLL circuit. The trigger circuitry is connected to an output terminal of an adjustable low-pass filter in the PLL circuit, and receives a proportional path output signal of the PLL circuit. Thereby, when a frequency deviation in the filtered SSC signal exceeds or crosses one or more thresholds, the trigger circuitry produces a trigger event.
Abstract translation: 要解决的问题：立即触发SSC信号的频率偏差dF / dT。 解决方案：在测试和测量仪器200的输入端210处接收的信号被低通滤波并被发送到dF / dT触发电路220.dF / dT触发电路220包括触发电路和PLL电路。 触发电路连接到PLL电路中可调低通滤波器的输出端，并接收PLL电路的比例路径输出信号。 因此，当滤波的SSC信号中的频率偏差超过或超过一个或多个阈值时，触发电路产生触发事件。 版权所有（C）2012，JPO＆INPIT
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公开(公告)号：JP2014039262A
公开(公告)日：2014-02-27
申请号：JP2013170226
申请日：2013-08-20
Applicant: Tektronix Inc , テクトロニクス・インコーポレイテッドTektronix,Inc.
Inventor： SMITH PATRICK A , KNIERIM DANIEL G
CPC classification number: H03K3/0315 , H03K3/0322
Abstract: PROBLEM TO BE SOLVED: To provide fine delays realizing gate delays shorter than one gate delay by coupling a plurality of multiplexers.SOLUTION: A ring oscillator timer circuit 10 includes a plurality of electrical components 16, 24, 32, 40, and 48 configured as cascaded combination of delay stages connected in a closed loop chain. The timer circuit 10 begins oscillation after a programmable number of unit gate delays after receiving a start signal. In some examples, fine delays smaller than the unit gate delays can be set. In further examples, the timer circuit 10 may include a counter having an input terminal electrically coupled to an output terminal of a reset electrical component.
Abstract translation: 要解决的问题：通过耦合多个复用器来提供实现比一个门延迟短的门延迟的精细延迟。解决方案：环形振荡器定时器电路10包括多个电组件16,24,32,40和48，其被配置为 连接在闭环链中的延迟级的级联组合。 在接收到起始信号之后，定时器电路10在可编程数量的单位门延迟之后开始振荡。 在一些示例中，可以设置小于单位门延迟的精细延迟。 在另外的示例中，定时器电路10可以包括具有电耦合到复位电气部件的输出端子的输入端子的计数器。
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公开(公告)号：JP2009109488A
公开(公告)日：2009-05-21
申请号：JP2008260111
申请日：2008-10-06
Applicant: Tektronix Inc , テクトロニクス・インコーポレイテッドTektronix,Inc.
Inventor： HAZZARD SHANE A , TRAN QUE THUY , KLINGMAN KAYLA R , KELLY DAVID L , SMITH PATRICK A , KNIERIM DANIEL G
IPC: G01R13/28
CPC classification number: H03M9/00 , H04J3/076 , H04L25/14 , H04L25/4908
Abstract: PROBLEM TO BE SOLVED: To improve the performance and flexibility of serial data analysis.
SOLUTION: In a transmitter section 10, a demultiplexer 12 inputs serial data and outputs n×N data lanes, an encoder 14 inputs these data lanes and generates m×N encoded data lanes, a circuit 16 inserts additional data into these encoded data lanes and generates m×N stuffed data lanes, and a multiplexer 18 inputs these stuffed data lanes and outputs N serial data lanes at a desired data rate. A receiver section 20 inputs N serial data lanes and outputs a trigger event for serial data.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：提高串行数据分析的性能和灵活性。 解决方案：在发射机部分10中，解复用器12输入串行数据并输出n×N个数据通道，编码器14输入这些数据通道并生成m×N个编码数据通道，电路16将附加数据插入到这些编码的 数据通道并产生m×N填充数据通道，并且多路复用器18输入这些填充的数据通道，并以期望的数据速率输出N个串行数据通道。 接收器部分20输入N个串行数据通道并输出用于串行数据的触发事件。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP2009124701A
公开(公告)日：2009-06-04
申请号：JP2008274745
申请日：2008-10-24
Applicant: Tektronix Inc , テクトロニクス・インコーポレイテッドTektronix,Inc.
Inventor： SMITH PATRICK A , KNIERIM DANIEL G
CPC classification number: G01R31/3171 , G01R13/0218 , H04L1/205 , H04L1/24
Abstract: PROBLEM TO BE SOLVED: To substantially eliminate the dead time related to futile searches by avoiding such futile searches for non-existent eye violations, while using an eye diagram for specifying the quality of a serial/digital signal.
SOLUTION: When detecting a violation due to a digital signal within a unit time interval while acquiring the digital signal, a mask 12 is defined within the unit time interval. When the digital signal crosses a master during a period of the unit time interval, a violation signal is generated.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：在使用眼图指定串行/数字信号的质量的同时，通过避免对不存在的眼睛违规的这种无效搜索，大大消除与无效搜索相关的死亡时间。 解决方案：当在获取数字信号的同时检测到在单位时间间隔内的数字信号的违规时，在单位时间间隔内定义掩模12。 当数字信号在单位时间间隔期间与主机交叉时，产生违规信号。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP2007155718A
公开(公告)日：2007-06-21
申请号：JP2006319146
申请日：2006-11-27
Applicant: Tektronix Inc , テクトロニクス・インコーポレイテッドTektronix,Inc.
Inventor： SMITH PATRICK A , WANZENRIED ROLAND E
IPC: G01R13/28
CPC classification number: G01R13/0254
Abstract: PROBLEM TO BE SOLVED: To provide triggering on detecting specific analog anomalies and/or digital data contained in a specific identification area of a serial data stream.
SOLUTION: A start word recognizer 16 detects a start pattern in the serial data stream to generate an enable signal. Then a stop word recognizer 18 detects a stop pattern in the serial data stream to generate a disable signal. An arm circuit 24 generates an identification signal which indicates a period between the enable signal and the disable signal. A trigger circuit 30 generates a trigger signal if detecting an analog anomaly and/or specific digital data generated during a period of the identification signal.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题：提供检测包含在串行数据流的特定识别区域中的特定模拟异常和/或数字数据的触发。 解决方案：起始字识别器16检测串行数据流中的起始模式以产生使能信号。 然后停止字识别器18检测串行数据流中的停止模式以产生禁用信号。 臂电路24产生指示使能信号和禁用信号之间的周期的识别信号。 触发电路30如果检测到在识别信号的周期期间产生的模拟异常和/或特定数字数据，则产生触发信号。 版权所有（C）2007，JPO＆INPIT
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