公开(公告)号：US4597029A

公开(公告)日：1986-06-24

申请号：US591342

申请日：1984-03-19

申请人： Andrzej Kucharek ,  John Marshall ,  James C. K. Lee ,  Carlton G. Amdahl ,  Leo Yuan

发明人： Andrzej Kucharek ,  John Marshall ,  James C. K. Lee ,  Carlton G. Amdahl ,  Leo Yuan

IPC分类号： H05K7/10 ,  H01R9/00

CPC分类号： H05K7/1053

摘要： A semiconductor chip having a two-dimensional array of contacts on an exposed face thereof is mounted in a semiconductor chip module. A mechanism for delivering electricity spans the exposed face of the chip to which it is connected and includes interstitial gaps. A conductor board has a surface proximate the electricity delivering mechanism opposite from the chip. The surface of the board has a two-dimensional array of contacts which correspond to at least some of the contacts on the chip. A biasing mechanism extends from the electricity delivering mechanism toward the exposed face of the semiconductor chip and toward the conductor board, and corresponds to the array of contacts on the chip and board. Signal leads pass through the interstitial gaps and have end portions which extend transversely over the biasing means. The end portions of the signal leads are biased against the contacts of the chips and board by the biasing mechanism.

摘要翻译： 在半导体芯片模块中安装有在其暴露表面上具有二维接触阵列的半导体芯片。 用于传递电力的机构跨越与其连接的芯片的暴露面并且包括间隙。 导体板具有与芯片相对的电力输送机构的表面。 板的表面具有对应于芯片上的至少一些触点的触点的二维阵列。 偏置机构从电力输送机构朝向半导体芯片的露出面朝向导体板延伸，并且对应于芯片和板上的触点阵列。 信号引线通过间隙隙并且具有在偏置装置上横向延伸的端部。 信号引线的端部通过偏置机构偏置在芯片和板的触点上。

公开(公告)号：US4748495A

公开(公告)日：1988-05-31

申请号：US763957

申请日：1985-08-08

申请人： Andrzej Kucharek

发明人： Andrzej Kucharek

IPC分类号： H01L23/433

CPC分类号： H01L23/4338 ,  H01L24/72 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/73251 ,  H01L24/16 ,  H01L2924/14 ,  H01L2924/3011

摘要： A package for mounting and cooling a high density array of integrated circuit chips includes an interconnection assembly for the IC chips which (1) provides base connections to a printed circuit board (PCB), which is adapted to connect to external signal circuits, and (2) separate peripheral power supply connections. The package also includes a cooling module containing fluid-cooled heat sinks that (a) collectively conform to the array of integrated circuit chips and (b) individually conform to the configuration and orientation of the individual chips. The heat sinks are conformed to the chip orientation independently of the coolant flow, which is established through the heat sinks immediately adjacent the interface. Among other aspects of the package, the interconnection assembly incorporates resilient connectors that provide essentially stress-impervious connections to the integrated circuit chips and to the signal PCB.

摘要翻译： 用于安装和冷却集成电路芯片的高密度阵列的封装包括用于IC芯片的互连组件，（1）提供与印刷电路板（PCB）的基本连接，印刷电路板适于连接到外部信号电路，以及（ 2）单独的外围电源连接。 该封装还包括一个包含流体冷却的散热器的冷却模块，其（a）统一地符合集成电路芯片的阵列，并且（b）分别符合各个芯片的配置和取向。 散热器不依赖于冷却剂流动而与芯片方向一致，冷却剂流通过紧邻界面的散热器建立。 在包装的其它方面中，互连组件包括弹性连接器，其提供基本上对集成电路芯片和信号PCB的应力不可渗透的连接。

公开(公告)号：US4943686A

公开(公告)日：1990-07-24

申请号：US182626

申请日：1988-04-18

申请人： Andrzej Kucharek

发明人： Andrzej Kucharek

IPC分类号： H05K5/06

CPC分类号： H05K5/061 ,  Y10T403/642

摘要： A sealing frame arrangement is disclosed for creating a hermetic seal between two components or bodies such as a connector and heat sink module of an integrated circuit package. The frame members are configured to fit together along facing surfaces and to be joined to the two bodies along the inner edge of their outside (non-facing) surfaces. The sealing arrangement is completed by a third seal formed along the outer facing edge of the frames. The frames extend a sufficient distance beyond the two components to permit severing the frames inside the third seal and resealing. Preferably, the frames are of sufficient width to provide a multiplicity of sealing regions so that the third seal can be broken and resealed a number of times. The seal frames may be of stepped or corrugated configuration in which the individual seals are formed along the mating steps.

摘要翻译： 公开了用于在诸如集成电路封装的连接器和散热器模块的两个部件或主体之间形成气密密封的密封框布置。 框架构件被构造成沿着相对的表面装配在一起，并且沿其外部（非面向）表面的内边缘连接到两个主体。 密封装置通过沿着框架的面向外边缘形成的第三密封完成。 框架延伸足够的距离超过两个部件，以允许切断第三密封件内的框架并重新密封。 优选地，框架具有足够的宽度以提供多个密封区域，使得第三密封件可以被破坏并重新密封多次。 密封框架可以是阶梯式或波纹形状，其中沿着配合步骤形成各个密封件。

公开(公告)号：US4603345A

公开(公告)日：1986-07-29

申请号：US590651

申请日：1984-03-19

申请人： James C. K. Lee ,  Gene M. Amdahl ,  Carlton G. Amdahl ,  Robert J. Beall ,  Anthony Matouk ,  John W. Sliwa ,  Andrzej Kucharek

发明人： James C. K. Lee ,  Gene M. Amdahl ,  Carlton G. Amdahl ,  Robert J. Beall ,  Anthony Matouk ,  John W. Sliwa ,  Andrzej Kucharek

IPC分类号： H01L23/34 ,  H01L23/473 ,  H01L23/50 ,  H01L23/46

CPC分类号： H01L23/473 ,  H01L23/50 ,  H01L2924/0002

摘要： A module for a semiconductor chip is disclosed. The module includes a heat sink with a flat surface to which the back face of the semiconductor chip is directly bonded. The exposed face of the chip has an array of power, ground and signal contacts. A plurality of alternating power and ground bus bars span the exposed face of the chip. A multilayer ceramic is located on the other side of the bus bar array and has a surface proximate the power and ground bus bars with an array of contacts which correspond to at least the signal contacts on the chip. Power leads connect the power bus bars to adjacent power contacts on the chip; ground leads connect the ground bus bars to adjacent ground contacts on the chip; and signal leads pass between adjacent power and ground bus bars and interconnect the signal contacts on the chip with the corresponding signal contacts on the ceramic. A plurality of connectors emanate from the ceramic and are electrically coupled by vias or traces through the ceramic to the signal contacts for the transmission of signals to and from the chip.

摘要翻译： 公开了一种用于半导体芯片的模块。 该模块包括具有平坦表面的散热器，半导体芯片的背面直接粘合在该散热器上。 芯片的暴露面具有电源，接地和信号触点阵列。 多个交流电源和接地母线跨越芯片的暴露面。 多层陶瓷位于母线阵列的另一侧，并且具有靠近电源和接地母线的表面，其具有至少对应于芯片上的信号触点的触点阵列。 电源引线将电源总线连接到芯片上的相邻电源触点; 接地引线将接地母线连接到芯片上的相邻接地触点; 并且信号引线在相邻的电源和接地母线之间通过，并将芯片上的信号触点与陶瓷上的相应信号触点相互连接。 多个连接器从陶瓷发出并且通过陶瓷的通孔或迹线电耦合到信号触头，以将信号传输到芯片和从芯片传输。