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公开(公告)号：US5847912A
公开(公告)日：1998-12-08
申请号：US642501
申请日：1996-05-03
申请人： Gregory J. Smith , Anthony D. Wang
发明人： Gregory J. Smith , Anthony D. Wang
CPC分类号： H02J7/0031
摘要： An active rectifier circuit for automatically selecting a pathway for reversible current to move. The rectifier circuit includes a transistor element that is preferably a MOSFET controlled by an amplifier. The amplifier is coupled to a reference voltage source that regulates operation of the transistor element at a potential much lower than is currently available with diode devices. In one application, the rectifier is a battery protection circuit for use within rechargeable battery packs. The battery protection circuit employs the amplifier to drive a pair of discrete MOSFETs having their sources coupled together. In this application, the amplifier functions as a sensitive current detector. The battery protection circuit automatically detects when any battery cell is over-charged or under-charged thereby opening and protecting the MOSFETs. The battery protection circuit determines the direction of current flow within the battery pack. It also automatically detects safe conditions for recovery from an over/under discharge or overcurrent conditions. Optional digital switches may be employed to regulate on, off, and direction of current flow permitted through the MOSFET pair, which effectively is a low-turn-on-threshold reversible diode.
摘要翻译： 一种用于自动选择可逆电流移动通路的有源整流电路。 整流电路包括优选由放大器控制的MOSFET的晶体管元件。 放大器耦合到参考电压源，该参考电压源以比二极管器件当前可用的电位低得多的电位来调节晶体管元件的工作。 在一个应用中，整流器是用于可充电电池组中的电池保护电路。 电池保护电路采用放大器来驱动一对具有耦合在一起的分立MOSFET。 在此应用中，放大器用作敏感电流检测器。 电池保护电路自动检测何时任何电池电池过充电或欠充电，从而打开和保护MOSFET。 电池保护电路确定电池组内电流的方向。 它还可以自动检测从过/欠放电或过电流条件恢复的安全条件。 可以采用可选的数字开关来调节通过MOSFET对允许的电流的导通，截止和方向，这有效地是低匝阈可逆二极管。
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公开(公告)号：US4897616A
公开(公告)日：1990-01-30
申请号：US223796
申请日：1988-07-25
申请人： Anthony D. Wang , R. Mark Stitt, II
发明人： Anthony D. Wang , R. Mark Stitt, II
CPC分类号： H03F3/3076 , H03F1/307
摘要： A wideband integrated circuit amplifier includes a pair of current mirror circuits sensing emitter currents of NPN and PNP transistors in the amplifier output stage. A pair of current mirror circuits divide the emitter currents, respectively, by a factor of 20. The current mirror output currents are summed, current splitter directs approximately 1/20 of the summed mirror currents through a transistor, the collector of which is coupled to the gate electrode of a field effect input transistor of a bias control circuit, to produce a scaled down feedback current. A high impedance current source is connected to the collector of the transistor. The bias circuit adjusts the DC bias voltage applied between the base electrodes of the transistors to cause the scaled down feedback current to equal the constant current. A very small compensation capacitor produces a low frequency pole that prevents the bias circuit from interfering with high frequency performance characteristics of a wide band amplifier.
摘要翻译： 宽带集成电路放大器包括一对在放大器输出级中感测NPN和PNP晶体管的发射极电流的电流镜电路。 一对电流镜电路分别将发射极电流分成20倍。电流反射镜输出电流相加，电流分流器将大约1/20的总和镜电流引导通过晶体管，其集电极耦合到 偏置控制电路的场效应输入晶体管的栅电极，以产生按比例缩小的反馈电流。 高阻抗电流源连接到晶体管的集电极。 偏置电路调节施加在晶体管的基极之间的直流偏置电压，使缩小的反馈电流等于恒定电流。 一个非常小的补偿电容产生一个低频极点，防止偏置电路干扰宽带放大器的高频性能特性。
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3.发明授权Complementary current mirror for correcting input offset voltage of diamond follower, especially as input stage for wide-band amplifier 失效用于校正金刚石跟随器的输入失调电压的互补电流镜，特别是作为宽带放大器的输入级
公开(公告)号：US4893091A
公开(公告)日：1990-01-09
申请号：US255774
申请日：1988-10-11
申请人： William J. Lillis , Anthony D. Wang
发明人： William J. Lillis , Anthony D. Wang
CPC分类号： H03F1/307 , H03F3/3001 , H03F3/3076
摘要： A complementary current mirror includes a PNP transistor and an NPN transistor, one of which serves as a control transistor and the other of which serves as an output transistor. A V.sub.BE voltage generated by forcing a control current into or out of the emitter of the control transistor is imposed between the base and emitter of the output transistor to produce a controlled current in the collector of the output transistor. A first such current mirror, with an NPN control transistor, and a second such current mirror, with a PNP control transistor, are driven by the same control current to supply first and second input bias currents to a diamond follower circuit in the same integrated circuit as the first and second current mirror circuits to face the V.sub.BE voltage of the PNP and NPN transistors of the diamond follower circuit to be equal despite variation in saturation currents of the PNP and NPN transistsors. This results in zero input offset for the diamond follower circuit.
摘要翻译： 互补电流镜包括PNP晶体管和NPN晶体管，其中一个用作控制晶体管，另一个用作输出晶体管。 通过在控制晶体管的发射极之间施加控制电流而产生的VBE电压被施加在输出晶体管的基极和发射极之间，以在输出晶体管的集电极中产生受控电流。 具有NPN控制晶体管的第一电流镜和具有PNP控制晶体管的第二电流镜由相同的控制电流驱动，以将第一和第二输入偏置电流提供给同一集成电路中的金刚石跟踪器电路 作为第一和第二电流镜电路，以面对PNP和NPN晶体管的VBE电压，即使PNP和NPN转换器的饱和电流有变化，相等。 这导致了金刚石跟踪器电路的零输入偏移。
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公开(公告)号：US4423409A
公开(公告)日：1983-12-27
申请号：US250868
申请日：1981-04-03
摘要： A digital-to-analog converter circuit includes an open-loop reference circuit for regulating a plurality of bit switch currents and utilizes a high-speed single-ended input interface network for level shifting digital input signals to the bit switches whereat the level shifted input signals switch against a substantially fixed threshold voltage. The single-ended input interface network includes a PNP input transistor coupled to an input terminal and coupled by a resistor to a regulated voltage. The PNP input transistor is coupled to a level shifting network including an emitter follower transistor and a zener junction biased by a current source. The threshold voltage is also developed by a level shifting network that includes a zener junction for compensating variations within the level shifting network of the single-ended input interface network.
摘要翻译： 数模转换器电路包括用于调节多个位开关电流的开环参考电路，并且利用高速单端输入接口网络将数字输入信号电平移位到位开关，其中电平转换输入 信号切换基本固定的阈值电压。 单端输入接口网络包括耦合到输入端并由电阻器耦合到调节电压的PNP输入晶体管。 PNP输入晶体管耦合到包括射极跟随器晶体管和由电流源偏置的齐纳结的电平移动网络。 门限电压也由包括用于补偿单端输入接口网络的电平转换网络内的变化的齐纳结的电平转换网络开发。
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5.发明授权Digital-to-analog converter having open-loop voltage reference for regulating bit switch currents 失效具有用于调节位开关电流的开环参考电压的数模转换器
公开(公告)号：US4381497A
公开(公告)日：1983-04-26
申请号：US250858
申请日：1981-04-03
摘要： An open-loop voltage reference circuit, adapted to regulate a plurality of bit switch currents within a digital-to-analog converter, includes a zener diode reference leg for developing a reference voltage. The reference leg also includes a base-emitter junction voltage multiplier for creating a compensating voltage having a temperature tracking coefficient that is equal and opposite to that of the zener diode junction voltage. The reference voltage developed by the reference leg is used to bias a temperature independent current within a slave leg, and a current mirror circuit mirrors the current within the slave leg for supplying a constant current to the reference leg. The magnitude of the reference voltage is reduced through a divider leg, and an emitter follower leg provides a low impedance bias voltage for driving the plurality of bit switch current sources. The open-loop voltage reference circuit is further adapted to compensate for second order errors caused by temperature induced variations in current gain and Early effect variations related to changes in the power supply voltage. A Gain Adjust feature is also provided for adjusting the bit switch currents without adversely affecting the regulation thereof.
摘要翻译： 适于调节数模转换器内的多个位开关电流的开环参考电路包括用于开发参考电压的齐纳二极管参考支路。 参考支路还包括基极 - 发射极结电压倍增器，用于产生具有与齐纳二极管结电压相同和相反的温度跟踪系数的补偿电压。 由参考支路产生的参考电压用于偏置从动支路内的独立于温度的电流，并且电流镜电路反映从动支路内的电流，以向参考支路提供恒定电流。 参考电压的幅度通过分路器脚减小，并且射极跟随器腿提供用于驱动多个位开关电流源的低阻抗偏置电压。 开环电压参考电路还适于补偿由温度引起的电流增益变化和与电源电压变化相关的早期效应变化引起的二阶误差。 还提供增益调整功能，用于调整位开关电流，而不会对其调节产生不利影响。
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6.发明授权Circuit and method for reducing non-linearity in analog output current due to waste current switching 失效用于减少由于废电流切换引起的模拟输出电流的非线性的电路和方法
公开(公告)号：US4521765A
公开(公告)日：1985-06-04
申请号：US491600
申请日：1983-05-04
CPC分类号： H03M1/0612 , H03M1/68 , H03M1/745 , H03M1/785
摘要： An integrated circuit digital to analog converter includes circuitry having first and second resistors in a R/2R resistor ladder which scales bit current contributions to an analog output current. Each of the first and second resistors have a respective terminal connected to the collector of a bit current transistor, the emitter of which is connected to the emitter of a waste current transistor. The digital to analog converter includes a metal ground voltage conductor having a "shared node" and a distributed resistance between one side of the shared node and a main ground voltage connection. The collector of the waste current transistor and a second terminal of the first resistor are both connected directly to the shared node. In operation, the waste current transistor switches waste current into the shared node, rather than into a separate waste current ground conductor. This results in substantially less voltage variation across the distributed resistance of the metal ground voltage conductor, and consequently lower non-linearity, than is the case if waste current is switched into the separate ground conductor.
摘要翻译： 集成电路数模转换器包括具有R / 2R电阻梯中的第一和第二电阻器的电路，其对比模拟输出电流的比特电流贡献。 第一和第二电阻器中的每一个具有连接到位电流晶体管的集电极的相应端子，其发射极连接到废电流晶体管的发射极。 数模转换器包括具有共享节点的金属接地电压导体和共享节点的一侧与主接地电压连接之间的分布电阻。 废电流晶体管的收集器和第一电阻器的第二端子都直接连接到共享节点。 在运行中，废电流晶体管将浪费电流切换到共享节点，而不是分成废电流接地导体。 这导致金属接地电压导体的分布电阻之间的电压变化实质上更小，因此与废电流切换到单独接地导体的情况相比，具有更低的非线性。
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7.发明授权
公开(公告)号：US4468652A
公开(公告)日：1984-08-28
申请号：US421506
申请日：1982-09-22
CPC分类号： H03M1/0612 , H03M1/68 , H03M1/745 , H03M1/785
摘要： A monolithic digital-to-analog converter integrated circuit is disclosed including a first plurality of more significant bit switches having scaled bit switch currents and including a second plurality of lesser significant bit switches, the output nodes of which are coupled to a ladder network which contributes a binary-weighted portion of each lesser significant bit switch current to the summed analog output current. First and second output conductors, separate and apart from one another, are used to couple the output nodes of the more significant bit switches and the output current of the ladder network, respectively, to the analog output current pad. First and second ground voltage pads are included for isolating waste current conducted by the more significant bit switches from currents returned by the ladder network to the ground voltage. The waste current nodes of the lesser significant bit switches are conducted to the same ground voltage pad that conducts the currents returned by the ladder network.
摘要翻译： 公开了一种单片数模转换器集成电路，其包括具有缩放比特开关电流的第一多个更高有效位开关，并且包括第二多个较低有效位开关，其输出节点耦合到梯形网络 每个较低有效位开关电流的二进制加权部分到求和的模拟输出电流。 第一和第二输出导体彼此分离和分开用于将更高有效位开关的输出节点和梯形网络的输出电流分别耦合到模拟输出电流焊盘。 包括第一和第二接地电压焊盘，用于将由梯形网络返回的电流传导到更高有效位开关的浪涌电流与接地电压隔离。 较低有效位开关的废电流节点传导到导通梯形网络返回的电流的同一接地电压焊盘。
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