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    Dynamic clock phase alignment between independent clock domains
    2.
    发明授权
    Dynamic clock phase alignment between independent clock domains 失效
    独立时钟域之间的动态时钟相位对准

    公开(公告)号：US07904741B2

    公开(公告)日：2011-03-08

    申请号：US11870985

    申请日：2007-10-11

    申请人： Steven John Baumgartner ,  Charles Porter Geer

    发明人： Steven John Baumgartner ,  Charles Porter Geer

    IPC分类号： G06F1/00 ,  G06F1/24 ,  G06F1/12

    CPC分类号： G06F1/12

    摘要： A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

    摘要翻译： 描述了一种设计结构，用于以最小的延迟动态地对齐独立时钟域中的时钟。 在优选实施例中，目的时钟域中的目的时钟域的数据时钟的多倍的参考时钟用于从源域采样数据采样信号。 采样数据用于确定数据采样信号在什么时间片上参考时钟信号正在改变，因此在数据时钟的时间片或相位的什么阶段可以对准时钟，以确保有效数据将在时钟域之间传输 。

    Dynamic Clock Phase Alignment Between Independent Clock Domains
    6.
    发明申请
    Dynamic Clock Phase Alignment Between Independent Clock Domains 失效
    独立时钟域之间的动态时钟相位对准

    公开(公告)号：US20080072093A1

    公开(公告)日：2008-03-20

    申请号：US11870985

    申请日：2007-10-11

    申请人： Steven John Baumgartner ,  Charles Porter Geer

    发明人： Steven John Baumgartner ,  Charles Porter Geer

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12

    摘要： A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

    摘要翻译： 描述了一种设计结构，用于以最小的延迟动态地对齐独立时钟域中的时钟。 在优选实施例中，目的时钟域中的目的时钟域的数据时钟的多倍的参考时钟用于从源域采样数据采样信号。 采样数据用于确定数据采样信号在什么时间片上参考时钟信号正在改变，因此在数据时钟的时间片或相位的什么阶段可以对准时钟，以确保有效数据将在时钟域之间传输 。

    Dynamic clock phase alignment between independent clock domains
    7.
    发明授权
    Dynamic clock phase alignment between independent clock domains 失效
    独立时钟域之间的动态时钟相位对准

    公开(公告)号：US07716514B2

    公开(公告)日：2010-05-11

    申请号：US11533065

    申请日：2006-09-19

    申请人： Steven John Baumgartner ,  Charles Porter Geer

    发明人： Steven John Baumgartner ,  Charles Porter Geer

    IPC分类号： G06F1/00 ,  G06F1/24 ,  H04L25/40

    CPC分类号： G06F1/12

    摘要： An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

    摘要翻译： 描述了用于以最小的等待时间来在独立时钟域中动态地对准时钟的装置和方法。 在优选实施例中，目的时钟域中的目的时钟域的数据时钟的多倍的参考时钟用于从源域采样数据采样信号。 采样数据用于确定数据采样信号在什么时间片上参考时钟信号正在改变，因此在数据时钟的时间片或相位的什么阶段可以对准时钟，以确保有效数据将在时钟域之间传输 。

    Dynamic Clock Phase Alignment Between Independent Clock Domains
    8.
    发明申请
    Dynamic Clock Phase Alignment Between Independent Clock Domains 失效
    独立时钟域之间的动态时钟相位对准

    公开(公告)号：US20080126566A1

    公开(公告)日：2008-05-29

    申请号：US11533065

    申请日：2006-09-19

    申请人： Steven John Baumgartner ,  Charles Porter Geer

    发明人： Steven John Baumgartner ,  Charles Porter Geer

    IPC分类号： G06F15/16

    CPC分类号： G06F1/12

    摘要： An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

    摘要翻译： 描述了用于以最小的等待时间来在独立时钟域中动态地对准时钟的装置和方法。 在优选实施例中，目的时钟域中的目的时钟域的数据时钟的多倍的参考时钟用于从源域采样数据采样信号。 采样数据用于确定数据采样信号在什么时间片上参考时钟信号正在改变，因此在数据时钟的时间片或相位的什么阶段可以对准时钟，以确保有效数据将在时钟域之间传输 。

    Dynamic repair of redundant memory array
    9.
    发明授权
    Dynamic repair of redundant memory array 有权
    冗余存储器阵列的动态修复

    公开(公告)号：US06181614B2

    公开(公告)日：2001-01-30

    申请号：US09439974

    申请日：1999-11-12

    申请人： Anthony Gus Aipperspach ,  Charles Porter Geer

    发明人： Anthony Gus Aipperspach ,  Charles Porter Geer

    IPC分类号： G11C700

    CPC分类号： G11C29/72 ,  G11C29/4401 ,  G11C2029/0407

    摘要： A circuit arrangement and method of dynamically repairing a redundant memory array utilize dynamically-determined repair information, generated from a memory test performed on the redundant memory array, along with persistently-stored repair information to repair the redundant memory array. In one implementation, for example, the persistent repair information is generated during manufacture to repair manufacturing defects in the array, with the dynamic repair information generated during a power-on reset of the array to address any additional faults arising after initial manufacture and repair of the array. Furthermore, repair of dynamically-determined errors may utilize otherwise unused redundant memory cells in a redundant memory array, thus minimizing the additional circuitry required to implement dynamic repair functionality with an array.

    摘要翻译： 动态修复冗余存储器阵列的电路装置和方法利用从对冗余存储器阵列执行的存储器测试产生的动态确定的修复信息，以及持续存储的修复信息来修复冗余存储器阵列。 在一个实现中，例如，在制造期间生成持久修复信息以修复阵列中的制造缺陷，其中在阵列的上电复位期间产生的动态修复信息以解决在初始制造和修复之后出现的任何附加故障 阵列。 此外，动态确定的错误的修复可以利用冗余存储器阵列中的未使用的冗余存储器单元，从而最小化利用阵列来实现动态修复功能所需的附加电路。

    Clock frequency detect with programmable jitter tolerance
    10.
    发明授权
    Clock frequency detect with programmable jitter tolerance 失效

    公开(公告)号：US07129757B2

    公开(公告)日：2006-10-31

    申请号：US11000439

    申请日：2004-11-30

    申请人： Charles Porter Geer ,  Robert Allen Shearer

    发明人： Charles Porter Geer ,  Robert Allen Shearer

    IPC分类号： G01R25/00

    CPC分类号： G01R23/005 ,  H03D13/00

    摘要： An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized with a first bit pattern and a second bit pattern, respectively. In a second, normal, mode, the first clock is coupled to the first register and the second clock is coupled to the second register. A compare unit observes the bit patterns of the first and second registers and reports when one or more predetermined relationships between the first clock and the second clock occur.