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    Container with cat motif
    2.
    外观设计
    Container with cat motif 有权

    公开(公告)号：USD1044512S1

    公开(公告)日：2024-10-01

    申请号：US29867828

    申请日：2022-11-09

    Applicant: David Tran

    Designer： David Tran

    Abstract: FIG. 1 is an isometric perspective view of a container with cat motif;
    FIG. 2 is a front elevation view thereof;
    FIG. 3 is a rear elevation view thereof;
    FIG. 4 is a top plan view thereof;
    FIG. 5 is a bottom plan view thereof;
    FIG. 6 is a left side elevation view thereof; and,
    FIG. 7 is a right side elevation view thereof.
    The broken lines shown in the drawings represent portions of the container with cat motif that form no part of the claimed design.

    Stationary holder with cat motif
    7.
    外观设计
    Stationary holder with cat motif 有权

    公开(公告)号：USD1038234S1

    公开(公告)日：2024-08-06

    申请号：US29882739

    申请日：2023-01-18

    Applicant: David Tran

    Designer： David Tran

    Abstract: FIG. 1 is an isometric perspective view of embodiment 1 of a stationary holder with cat motif;
    FIG. 2 is a front elevation view thereof;
    FIG. 3 is a rear elevation view thereof;
    FIG. 4 is a left side elevation view thereof;
    FIG. 5 is a right side elevation view thereof;
    FIG. 6 is a top plan view thereof; and
    FIG. 7 is a bottom plan view thereof.
    FIG. 8 is an isometric perspective view of embodiment 2;
    FIG. 9 is a front elevation view of embodiment 2;
    FIG. 10 is a rear elevation view of embodiment 2;
    FIG. 11 is left side elevation of embodiment 2;
    FIG. 12 is right side elevation of embodiment 2;
    FIG. 13 is a top plan view of embodiment 2; and,
    FIG. 14 is a bottom plan view of embodiment 2.
    The broken lines shown in the drawings represent portions of the stationary holder with cat motif that form no part of the claimed design.

    Multiplicative division circuit with reduced area
    9.
    发明授权
    Multiplicative division circuit with reduced area 有权
    具有减小面积的乘法除法电路

    公开(公告)号：US08819094B2

    公开(公告)日：2014-08-26

    申请号：US12488956

    申请日：2009-06-22

    Applicant: Kyung-Nam Han ,  Alexandre Tenca ,  David Tran ,  Rick Kelly

    Inventor： Kyung-Nam Han ,  Alexandre Tenca ,  David Tran ,  Rick Kelly

    IPC: G06F7/38

    CPC classification number: G06F7/535 ,  G06F2207/5355

    Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

    Abstract translation: 该技术是电路面积减小的分频电路。 实施例包括实现分红输入和除数输入的乘法除法的集成电路。 集成电路包括查找表电路和乘法器电路。 查找表电路提供除数输入的倒数的近似值。 乘法器电路接收近似值并优化除数输入的商输出和除数输入。 乘法器电路中的至少一个是实现与减少数量的中间部分乘积相乘的平方电路。 减少的中间部分积的数量防止平方电路与任何两个不相等的数字相乘，并且将平方电路限制为相同数量的乘法相同的数字。

    Multiplicative Division Circuit With Reduced Area
    10.
    发明申请
    Multiplicative Division Circuit With Reduced Area 有权
    具有缩小面积的乘法分割电路

    公开(公告)号：US20100318592A1

    公开(公告)日：2010-12-16

    申请号：US12488956

    申请日：2009-06-22

    Applicant: Kyung-Nam Han ,  Alexandre Tenca ,  David Tran ,  Rick Kelly

    Inventor： Kyung-Nam Han ,  Alexandre Tenca ,  David Tran ,  Rick Kelly

    IPC: G06F7/52 ,  G06F17/50

    CPC classification number: G06F7/535 ,  G06F2207/5355

    Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

    Abstract translation: 该技术是电路面积减小的分频电路。 实施例包括实现分红输入和除数输入的乘法除法的集成电路。 集成电路包括查找表电路和乘法器电路。 查找表电路提供除数输入的倒数的近似值。 乘法器电路接收近似值并优化除数输入的商输出和除数输入。 乘法器电路中的至少一个是实现与减少数量的中间部分乘积相乘的平方电路。 减少的中间部分积的数量防止平方电路与任何两个不相等的数字相乘，并且将平方电路限制为相同数量的乘法相同的数字。

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