公开(公告)号：US20170077117A1

公开(公告)日：2017-03-16

申请号：US14853783

申请日：2015-09-14

申请人： SRI SAI SIVAKUMAR VEGUNTA ,  GOWRISANKAR DAMARLA ,  JIAN ZHOU

发明人： SRI SAI SIVAKUMAR VEGUNTA ,  GOWRISANKAR DAMARLA ,  JIAN ZHOU

IPC分类号： H01L27/115 ,  G06F3/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3213

CPC分类号： H01L27/11582 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L27/1157 ,  H01L27/11573

摘要： A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.

摘要翻译： 描述了具有阵列区域和外围区域的三维存储器件。 阵列区域具有存储单元的三维堆叠。 周边区域具有从存储单元的三维堆叠的上方延伸到存储单元的三维堆叠下方的触点。 外围区域基本上没有存储单元的三维堆叠的导电和/或半导体层。

公开(公告)号：US09263459B1

公开(公告)日：2016-02-16

申请号：US14498673

申请日：2014-09-26

申请人： Hongqi Li ,  Gowrisankar Damarla ,  Roger Lindsay ,  Zailong Bian ,  Jin Lu ,  Shyam Ramalingam ,  Prasanna Srinivasan

发明人： Hongqi Li ,  Gowrisankar Damarla ,  Roger Lindsay ,  Zailong Bian ,  Jin Lu ,  Shyam Ramalingam ,  Prasanna Srinivasan

IPC分类号： H01L21/8226 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/336 ,  H01L29/66 ,  H01L27/115

CPC分类号： H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556

摘要： A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.

摘要翻译： 三维或堆叠电路器件包括在导体通道上的导电通道盖。 可以通过选择性沉积或其它工艺来产生通道盖，以防止抛光导电材料以隔离触点。 导体通道延伸穿过通过门激活的多层电路元件。 门通过导体通道中的电位激活。 导体通道上的导电盖可以将导体通道电连接到位线或其他信号线，和/或电连接到多个电路元件的另一层。