公开(公告)号：US07860202B2

公开(公告)日：2010-12-28

申请号：US11402800

申请日：2006-04-13

申请人： Gyh-Bin Wang ,  Hsien-Sheng Huang

发明人： Gyh-Bin Wang ,  Hsien-Sheng Huang

IPC分类号： H04L7/00

CPC分类号： H04L7/00 ,  G09G3/20 ,  G09G2310/0267 ,  G09G2310/0275 ,  H04L7/0045 ,  H04L7/005

摘要： The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream, which comprises N parallel signals divided into a first group of parallel signals and a second group of parallel signals, to be in accordance with a first sequence of N sampling pulses, and a sampling module sequentially samples each signal in the first group signals and the second group signals with the N sampling pulses in a second sequence and outputs a serial signal.

摘要翻译： 该方法和电路提供了一个有效的实现来处理多个时钟域之间的数据传输问题。 移位电路将包括划分成第一组并行信号的N个并行信号和第二组并行信号的输入数据流移位为与N个采样脉冲的第一序列相对应，并且采样模块顺序地对每个 第一组信号中的信号和具有N个采样脉冲的第二组信号以第二序列输出，并输出串行信号。

公开(公告)号：US07750683B2

公开(公告)日：2010-07-06

申请号：US12252329

申请日：2008-10-15

申请人： Hsien-Sheng Huang ,  Feng-Chia Chang

发明人： Hsien-Sheng Huang ,  Feng-Chia Chang

IPC分类号： H03D13/00

CPC分类号： H03D13/00 ,  H03L7/089

摘要： PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

摘要翻译： PFD包括UP和DOWN信号模块以及RESET信号模块。 UP和DOWN信号模块根据参考和反馈时钟信号发送UP和DOWN信号。 RESET模块包括UP-RESET和DOWN-RESET信号模块。 UP-RESET信号模块根据预触发反馈信号，UP和DOWN信号复位UP信号模块。 根据原始反馈时钟信号和逻辑门和反相延迟模块的计算产生预触发反馈信号。 DOWN-RESET信号模块根据预触发参考信号，UP和DOWN信号复位DOWN信号模块。 根据原始参考时钟信号和逻辑门和反相延迟模块的计算产生预触发参考信号。

公开(公告)号：US20100019802A1

公开(公告)日：2010-01-28

申请号：US12252329

申请日：2008-10-15

申请人： Hsien-Sheng Huang ,  Feng-Chia Chang

发明人： Hsien-Sheng Huang ,  Feng-Chia Chang

IPC分类号： H03D13/00

CPC分类号： H03D13/00 ,  H03L7/089

摘要： PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

摘要翻译： PFD包括UP和DOWN信号模块以及RESET信号模块。 UP和DOWN信号模块根据参考和反馈时钟信号发送UP和DOWN信号。 RESET模块包括UP-RESET和DOWN-RESET信号模块。 UP-RESET信号模块根据预触发反馈信号，UP和DOWN信号复位UP信号模块。 根据原始反馈时钟信号和逻辑门和反相延迟模块的计算产生预触发反馈信号。 DOWN-RESET信号模块根据预触发参考信号，UP和DOWN信号复位DOWN信号模块。 根据原始参考时钟信号和逻辑门和反相延迟模块的计算产生预触发参考信号。

公开(公告)号：US20080231333A1

公开(公告)日：2008-09-25

申请号：US11758012

申请日：2007-06-05

申请人： Hsien-Sheng Huang

发明人： Hsien-Sheng Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/16 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18

摘要： A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum.

摘要翻译： 公开了一种扩频时钟发生器。 扩频时钟发生器（SSCG）基于锁相环的结构。 SSCG使用具有多相输出功能的电压控制振荡器来输出不同相位的时钟信号。 不同相位的时钟信号被选择性地反馈到相位频率检测器。 以这种方式，改变输出信号的频率，实现扩展频谱。

公开(公告)号：US07446578B2

公开(公告)日：2008-11-04

申请号：US11758012

申请日：2007-06-05

申请人： Hsien-Sheng Huang

发明人： Hsien-Sheng Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/16 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18

摘要： A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum.

摘要翻译： 公开了一种扩频时钟发生器。 扩频时钟发生器（SSCG）基于锁相环的结构。 SSCG使用具有多相输出功能的电压控制振荡器来输出不同相位的时钟信号。 不同相位的时钟信号被选择性地反馈到相位频率检测器。 以这种方式，改变输出信号的频率，实现扩展频谱。

公开(公告)号：US20100033217A1

公开(公告)日：2010-02-11

申请号：US12253211

申请日：2008-10-16

申请人： Chun Shiah ,  Chun-Peng Wu ,  Hsien-Sheng Huang

发明人： Chun Shiah ,  Chun-Peng Wu ,  Hsien-Sheng Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0802 ,  H03L7/0891

摘要： A DLL with power-saving function includes a VCDL, a voltage control module, a capacitor, and a phase detector. The VCDL generates a delayed clock signal according to the voltage on the capacitor and a reference clock signal. The phase detector detects phase difference between the delayed clock signal and the reference clock signal and accordingly controls the voltage controller. The voltage controller sinks or sources current to the capacitor for adjusting the voltage on the capacitor. Further, the voltage controller can turn off its charge pump according to a turned-off signal and stops sinking or sourcing current for saving power.

摘要翻译： 具有省电功能的DLL包括VCDL，电压控制模块，电容器和相位检测器。 VCDL根据电容器上的电压和参考时钟信号产生延迟的时钟信号。 相位检测器检测延迟时钟信号和参考时钟信号之间的相位差，因此控制电压控制器。 电压控制器将电流吸收或输出到电容器以调节电容器上的电压。 此外，电压控制器可以根据关闭信号关闭其电荷泵，并停止下沉或采集电流以节省电力。

公开(公告)号：US20090262879A1

公开(公告)日：2009-10-22

申请号：US12203919

申请日：2008-09-04

申请人： Hsien-Sheng Huang

发明人： Hsien-Sheng Huang

IPC分类号： H03D3/24

CPC分类号： H03L3/00 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/093 ,  H03L7/10

摘要： A delay-locked loop (DLL) circuit. In the evaluation period, the DLL circuit adjusts needed delay period of time for a reference clock signal by adjusting the amount of the used delay units which each of has fixed delay period of time digitally and controlling the delay period of time of the voltage control delay circuit analogically. In the locking period, the DLL circuit utilizes the delay time of the delay units, which is decided in the evaluation period, along with the voltage control delay circuit, to lock phase of the reference clock signal. In this way, the stability of the delay period of time of the voltage control delay circuit increases.

摘要翻译： 延迟锁定环（DLL）电路。 在评估期间，DLL电路通过调整每个具有数字固定的延迟时间的所使用的延迟单元的量并且控制电压控制延迟的延迟时间段来调整参考时钟信号所需的延迟时间段 电路类似。 在锁定期间，DLL电路利用在评估期间决定的延迟单元的延迟时间以及电压控制延迟电路来锁定参考时钟信号的相位。 以这种方式，电压控制延迟电路的延迟时间的稳定性增加。

公开(公告)号：US07414448B2

公开(公告)日：2008-08-19

申请号：US11503064

申请日：2006-08-14

申请人： Hsien-Sheng Huang ,  Chun Shiah

发明人： Hsien-Sheng Huang ,  Chun Shiah

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03L7/0812

摘要： A duty cycle correction circuit comprises a tuned circuit, a delay circuit and a phase-locked loop; wherein the tuned circuit receives an input clock, generates a periodic pulse according to the input clock, tunes the periodic pulse depending on a reference voltage, and outputs an output clock; a delay circuit receives the output clock, and generates a complementary signal; a phase lock loop receives the complementary signal, measures the periods of time of the high level state and the low level state of the complementary signal, generates the reference voltage and feeds back to the tuned circuit. By using the technique of the present invention, it is able to track the delay time between the input clock and the output clock, and the drift of the output clock is reduced.

摘要翻译： 占空比校正电路包括调谐电路，延迟电路和锁相环; 其中所述调谐电路接收输入时钟，根据所述输入时钟产生周期脉冲，根据参考电压调谐周期性脉冲，并输出输出时钟; 延迟电路接收输出时钟，并产生互补信号; 锁相环接收互补信号，测量互补信号的高电平状态和低电平状态的时间段，产生参考电压并反馈到调谐电路。 通过使用本发明的技术，能够跟踪输入时钟与输出时钟之间的延迟时间，并减小输出时钟的漂移。

公开(公告)号：US20080036517A1

公开(公告)日：2008-02-14

申请号：US11503064

申请日：2006-08-14

申请人： Hsien-Sheng Huang ,  Chun Shiah

发明人： Hsien-Sheng Huang ,  Chun Shiah

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03L7/0812

摘要： A duty cycle correction circuit comprises a tuned circuit, a delay circuit and a phase-locked loop; wherein the tuned circuit receives an input clock, generates a periodic pulse according to the input clock, tunes the periodic pulse depending on a reference voltage, and outputs an output clock; a delay circuit receives the output clock, and generates a complementary signal; a phase lock loop receives the complementary signal, measures the periods of time of the high level state and the low level state of the complementary signal, generates the reference voltage and feeds back to the tuned circuit. By using the technique of the present invention, it is able to track the delay time between the input clock and the output clock, and the drift of the output clock is reduced.

公开(公告)号：US20070257877A1

公开(公告)日：2007-11-08

申请号：US11402800

申请日：2006-04-13

申请人： Ghy-Bin Wang ,  Hsien-Sheng Huang

发明人： Ghy-Bin Wang ,  Hsien-Sheng Huang

IPC分类号： G09G3/36 ,  H04L7/00

CPC分类号： H04L7/00 ,  G09G3/20 ,  G09G2310/0267 ,  G09G2310/0275 ,  H04L7/0045 ,  H04L7/005

摘要： The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream and a sampling module sequentially samples and outputs each signal in the first group signals and the second group signals by the N sampling pulses with a sequence.

摘要翻译： 该方法和电路提供了一个有效的实现来处理多个时钟域之间的数据传输问题。 移位电路移动输入数据流，并且采样模块通过具有序列的N个采样脉冲顺序采样并输出第一组信号和第二组信号中的每个信号。