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    OUTPUT STAGE CIRCUIT FOR OUTPUTTING A DRIVING CURRENT VARYING WITH A PROCESS
    1.
    发明申请
    OUTPUT STAGE CIRCUIT FOR OUTPUTTING A DRIVING CURRENT VARYING WITH A PROCESS 有权
    用于输出驱动电流变化的输出电路

    公开(公告)号：US20120229174A1

    公开(公告)日：2012-09-13

    申请号：US13099380

    申请日：2011-05-03

    申请人： Chun Shiah ,  Hao-Jan Yang ,  Ching-Ying Hsu

    发明人： Chun Shiah ,  Hao-Jan Yang ,  Ching-Ying Hsu

    IPC分类号： H03K3/00

    CPC分类号： H03K19/018521 ,  H03K19/09482

    摘要： An output stage circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, and a current source. A voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor is a first voltage minus a voltage drop between a first terminal and a second terminal of the first P-type metal-oxide-semiconductor transistor. The N-type metal-oxide-semiconductor transistor is coupled between the third terminal of the first P-type metal-oxide-semiconductor transistor and the current source. A second terminal of the second P-type metal-oxide-semiconductor transistor is coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor. When a second terminal of the N-type metal-oxide-semiconductor transistor receives a kick signal, a driving current flowing through the second P-type metal-oxide-semiconductor transistor is relevant to the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor.

    摘要翻译： 输出级电路包括第一P型金属氧化物半导体晶体管，第二P型金属氧化物半导体晶体管，N型金属氧化物半导体晶体管和电流源。 第一P型金属氧化物半导体晶体管的第三端子的电压是第一电压减去第一P型金属氧化物半导体晶体管的第一端子和第二端子之间的电压降。 N型金属氧化物半导体晶体管耦合在第一P型金属氧化物半导体晶体管的第三端子与电流源之间。 第二P型金属氧化物半导体晶体管的第二端子耦合到第一P型金属氧化物半导体晶体管的第三端子。 当N型金属氧化物半导体晶体管的第二端子接收到反冲信号时，流过第二P型金属氧化物半导体晶体管的驱动电流与第一P型金属氧化物半导体晶体管的第三端子的电压相关， 型金属氧化物半导体晶体管。

    INPUT BUFFER SYSTEM WITH A DUAL-INPUT BUFFER SWITCHING FUNCTION AND METHOD THEREOF
    2.
    发明申请
    INPUT BUFFER SYSTEM WITH A DUAL-INPUT BUFFER SWITCHING FUNCTION AND METHOD THEREOF 有权
    具有双输入缓冲器切换功能的输入缓冲器系统及其方法

    公开(公告)号：US20120169371A1

    公开(公告)日：2012-07-05

    申请号：US13105891

    申请日：2011-05-11

    申请人： Chun Shiah ,  Sen-Fu Hong ,  Chia-Ming Chen

    发明人： Chun Shiah ,  Sen-Fu Hong ,  Chia-Ming Chen

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509

    摘要： An input buffer system with a dual-input buffer switching function includes a first input buffer, a second input buffer, and a multiplexer. The first input buffer is used for outputting a first signal when an input signal is at a logic-high voltage, and the first input buffer is turned off when the input signal is at a logic-low voltage. The second input buffer is used for outputting a second signal when the input signal is at the logic-low voltage. The multiplexer is coupled to the first input buffer and the second input buffer for outputting the first signal or the second signal according to a self refresh signal.

    摘要翻译： 具有双输入缓冲器切换功能的输入缓冲器系统包括第一输入缓冲器，第二输入缓冲器和多路复用器。 当输入信号处于逻辑高电压时，第一输入缓冲器用于输出第一信号，并且当输入信号处于逻辑低电压时，第一输入缓冲器被关断。 当输入信号处于逻辑低电压时，第二输入缓冲器用于输出第二信号。 复用器耦合到第一输入缓冲器和第二输入缓冲器，用于根据自刷新信号输出第一信号或第二信号。

    Method to improve the write speed for memory products
    4.
    发明申请
    Method to improve the write speed for memory products 有权

    公开(公告)号：US20100214856A1

    公开(公告)日：2010-08-26

    申请号：US12799335

    申请日：2010-04-22

    申请人： Chun Shiah

    发明人： Chun Shiah

    IPC分类号： G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/1006 ,  G11C2207/002

    摘要： A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip.

    Method to improve the write speed for memory products
    5.
    发明申请
    Method to improve the write speed for memory products 有权
    提高内存产品写入速度的方法

    公开(公告)号：US20090147596A1

    公开(公告)日：2009-06-11

    申请号：US11999799

    申请日：2007-12-07

    申请人： Chun Shiah

    发明人： Chun Shiah

    IPC分类号： G11C7/06

    CPC分类号： G11C7/065 ,  G11C7/1006 ,  G11C2207/002

    摘要： A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip.

    摘要翻译： 给出了一种方法和电路，用于实现具有用于以CMOS技术制造的集成电路（IC）的随机存取存储器（RAM）产品的数据线位开关（BS）传递晶体管的位线检测放大器，具有所述 RAM产品相对于良好的写入稳定性和高写入速度，并且其中BS FET开关的布局面积以及因此的芯片尺寸最小化。 这通过使用用于芯片的关键内部电路部分的氧化物层的两种厚度技术来实现。

    Input buffer system with a dual-input buffer switching function and method thereof
    6.
    发明授权
    Input buffer system with a dual-input buffer switching function and method thereof 有权
    具有双输入缓冲区切换功能的输入缓冲系统及其方法

    公开(公告)号：US08653855B2

    公开(公告)日：2014-02-18

    申请号：US13105891

    申请日：2011-05-11

    申请人： Chun Shiah ,  Sen-Fu Hong ,  Chia-Ming Chen

    发明人： Chun Shiah ,  Sen-Fu Hong ,  Chia-Ming Chen

    IPC分类号： H03K19/094

    CPC分类号： H03K19/017509

    摘要： An input buffer system with a dual-input buffer switching function includes a first input buffer, a second input buffer, and a multiplexer. The first input buffer is used for outputting a first signal when an input signal is at a logic-high voltage, and the first input buffer is turned off when the input signal is at a logic-low voltage. The second input buffer is used for outputting a second signal when the input signal is at the logic-low voltage. The multiplexer is coupled to the first input buffer and the second input buffer for outputting the first signal or the second signal according to a self refresh signal.

    摘要翻译： 具有双输入缓冲器切换功能的输入缓冲器系统包括第一输入缓冲器，第二输入缓冲器和多路复用器。 当输入信号处于逻辑高电压时，第一输入缓冲器用于输出第一信号，并且当输入信号处于逻辑低电压时，第一输入缓冲器被关断。 当输入信号处于逻辑低电压时，第二输入缓冲器用于输出第二信号。 复用器耦合到第一输入缓冲器和第二输入缓冲器，用于根据自刷新信号输出第一信号或第二信号。

    POWER-UP INITIAL CIRCUIT
    7.
    发明申请
    POWER-UP INITIAL CIRCUIT 有权
    上电初始电路

    公开(公告)号：US20130033250A1

    公开(公告)日：2013-02-07

    申请号：US13557235

    申请日：2012-07-25

    申请人： Yen-An Chang ,  Hao-Jan Yang ,  Chun Shiah

    发明人： Yen-An Chang ,  Hao-Jan Yang ,  Chun Shiah

    IPC分类号： G05F3/02

    CPC分类号： H03K17/162 ,  H03K2217/0081

    摘要： A power-up initial circuit includes a power-up control unit, a first switch and a second switch. The power-up control unit is used for receiving a high voltage start-up signal, and generating a first power-up control signal. The first switch has a first terminal for receiving an external voltage, a second terminal for coupling to the power-up control circuit for receiving the first power-up control signal, and a third terminal. The second switch has a first terminal coupled to the third terminal of the first switch, a second terminal for coupling to the power-up control circuit for receiving the first power-up control signal, and a third terminal for coupling to a high voltage generator.

    摘要翻译： 上电初始电路包括上电控制单元，第一开关和第二开关。 上电控制单元用于接收高电压启动信号，并产生第一上电控制信号。 第一开关具有用于接收外部电压的第一端子，用于耦合到用于接收第一上电控制信号的上电控制电路的第二端子和第三端子。 第二开关具有耦合到第一开关的第三端子的第一端子，用于耦合到用于接收第一上电控制信号的上电控制电路的第二端子，以及用于耦合到高电压发生器的第三端子 。

    Data detecting apparatus and methods thereof
    8.
    发明授权
    Data detecting apparatus and methods thereof 有权
    数据检测装置及其方法

    公开(公告)号：US07983102B2

    公开(公告)日：2011-07-19

    申请号：US12579920

    申请日：2009-10-15

    申请人： Shih-Hsing Wang ,  Der-Min Yuan ,  Bor-Doou Rong ,  Chun Shiah

    发明人： Shih-Hsing Wang ,  Der-Min Yuan ,  Bor-Doou Rong ,  Chun Shiah

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/08

    摘要： A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.

    摘要翻译： 在本发明的实施例中公开了一种数据检测装置和数据检测方法。 数据检测装置根据具有预定周期的时钟信号进行操作。 数据检测装置包括多个存储单元，多个数据线，多个位线，多个读出放大器和预充电控制电路。

    Delay Circuit
    10.
    发明申请
    Delay Circuit 审中-公开
    延时电路

    公开(公告)号：US20100019819A1

    公开(公告)日：2010-01-28

    申请号：US12252347

    申请日：2008-10-15

    申请人： Chun-Peng Wu ,  Chun Shiah ,  Feng-Chia Chang

    发明人： Chun-Peng Wu ,  Chun Shiah ,  Feng-Chia Chang

    IPC分类号： H03H11/26

    CPC分类号： H03K5/13 ,  H03K2005/00078 ,  H03K2005/00156

    摘要： Constant delay circuit includes signal input end, delay signal output end, RC delay circuit, and a comparator. The signal input end receives an input signal. The delay signal output end outputs the delay input signal, which the delay period is predetermined. The RC delay circuit is coupled to the signal input end for receiving the input signal and generating a voltage. The comparator includes a first input end, a second input end, and an output end. The first end of the comparator is coupled to the RC delay circuit for receiving the voltage. The second end of the comparator receives a reference voltage. The output end of the comparator is coupled to the delay signal output end of the long delay circuit. The comparator compares the reference voltage and the voltage, and accordingly generates a result as the delay signal.

    摘要翻译： 恒定延迟电路包括信号输入端，延迟信号输出端，RC延迟电路和比较器。 信号输入端接收输入信号。 延迟信号输出端输出预定延迟时间的延迟输入信号。 RC延迟电路耦合到信号输入端，用于接收输入信号并产生电压。 比较器包括第一输入端，第二输入端和输出端。 比较器的第一端耦合到用于接收电压的RC延迟电路。 比较器的第二端接收参考电压。 比较器的输出端耦合到长延迟电路的延迟信号输出端。 比较器比较参考电压和电压，并因此产生作为延迟信号的结果。