公开(公告)号：US20060212734A1

公开(公告)日：2006-09-21

申请号：US11315171

申请日：2005-12-23

Applicant: Chih-Cheng Han ,  Ming-Jiun Change ,  Hsuan-Ching Chao ,  Chung-Hong Lai

Inventor： Chih-Cheng Han ,  Ming-Jiun Change ,  Hsuan-Ching Chao ,  Chung-Hong Lai

IPC: G06F1/26

CPC classification number: G06F1/325 ,  G06F1/3203

Abstract: A method for transmitting a power-saving command between a computer system and system chips thereof is described. A power-saving command associated with a first system chip is introduced to the computer system since a BIOS is modified therefore. The CPU of the computer system determines the power mode of the first system chip according to a register therein. As the first system chip enters the power-saving mode, the second system chip is informed entering the power-saving mode as well. Therefore, the peripheral devices coupled to the system chips can enter the power-saving mode smoothly so as to solve that the devices cannot enter the mode simultaneously since there is no power management unit (PMU) installed in the first system chip.

Abstract translation: 描述了在计算机系统及其系统芯片之间发送节电命令的方法。 与第一系统芯片相关联的省电命令被引入到计算机系统，因为BIOS被修改。 计算机系统的CPU根据其中的寄存器来确定第一系统芯片的功率模式。 当第一个系统芯片进入省电模式时，第二个系统芯片也被通知进入省电模式。 因此，耦合到系统芯片的外围设备可以平滑地进入省电模式，以解决设备不能同时进入模式，因为在第一系统芯片中没有安装电源管理单元（PMU）。

公开(公告)号：US07469349B2

公开(公告)日：2008-12-23

申请号：US11315170

申请日：2005-12-23

Applicant: Chih-Cheng Han ,  Ming-Jiun Chang ,  Hsuan-Ching Chao ,  Chung-Hong Lai

Inventor： Chih-Cheng Han ,  Ming-Jiun Chang ,  Hsuan-Ching Chao ,  Chung-Hong Lai

IPC: G06F1/26

CPC classification number: G06F1/325 ,  G06F1/3203 ,  Y02D50/20

Abstract: A computer system and a method of signal transmission via a PCI-Express bus is provided for transmitting a power-saving signal among a plurality of peripheral devices. For the peripheral devices coupled with the system chips can enter a power-saving mode successfully, a signal snooping and blocking manners are introduced into the system chips. The present invention is to improve on a problem that the system chips cannot enter the power-saving mode simultaneously since the system chips don't set any power-management unit therein.

Abstract translation: 提供了一种通过PCI-Express总线进行信号传输的计算机系统和方法，用于在多个外围设备之间传输功率节省信号。 对于与系统芯片耦合的外围设备，可以成功进入省电模式，将信号窥探和阻塞方式引入系统芯片。 本发明是为了改进系统芯片不能同时进入省电模式的问题，因为系统芯片不在其中设置任何电源管理单元。

公开(公告)号：US20060212731A1

公开(公告)日：2006-09-21

申请号：US11315170

申请日：2005-12-23

Applicant: Chih-Cheng Han ,  Ming-Jiun Chang ,  Hsuan-Ching Chao ,  Chung-Hong Lai

Inventor： Chih-Cheng Han ,  Ming-Jiun Chang ,  Hsuan-Ching Chao ,  Chung-Hong Lai

IPC: G06F1/26

CPC classification number: G06F1/325 ,  G06F1/3203 ,  Y02D50/20

Abstract: A computer system and a method of signal transmission via a PCI-Express bus is provided for transmitting a power-saving signal among a plurality of peripheral devices. For the peripheral devices coupled with the system chips can enter a power-saving mode successfully, a signal snooping and blocking manners are introduced into the system chips. The present invention is to improve on a problem that the system chips cannot enter the power-saving mode simultaneously since the system chips don't set any power-management unit therein.

Abstract translation: 提供了一种通过PCI-Express总线进行信号传输的计算机系统和方法，用于在多个外围设备之间传输功率节省信号。 对于与系统芯片耦合的外围设备，可以成功进入省电模式，将信号窥探和阻塞方式引入系统芯片。 本发明是为了改进系统芯片不能同时进入省电模式的问题，因为系统芯片不在其中设置任何电源管理单元。

公开(公告)号：US20120079161A1

公开(公告)日：2012-03-29

申请号：US13233008

申请日：2011-09-14

Applicant: Hsuan-Ching Chao ,  Cheng-Pin Huang ,  Yu-Chiun Lin ,  Chia-Chun Chiang

Inventor： Hsuan-Ching Chao ,  Cheng-Pin Huang ,  Yu-Chiun Lin ,  Chia-Chun Chiang

IPC: G06F13/36

CPC classification number: G06F11/221

Abstract: A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus.

Abstract translation: 用于同时分析性能和错误的电路包括映射单元和USB 3.0数据流分析器。 映射单元用于映射通过USB 3.0主机的外围组件互连快速和内部事件传输到USB 3.0主机的命令到USB 3.0总线的数据包。 USB 3.0数据流分析仪用于通过USB 3.0总线的数据包分析USB 3.0主机的性能和错误。

公开(公告)号：US20110293055A1

公开(公告)日：2011-12-01

申请号：US13050968

申请日：2011-03-18

Applicant: Huei-Chiang Shiu ,  Hsuan-Ching Chao ,  Kuo-Cyuan Kuo ,  Ming-Kia Chen

Inventor： Huei-Chiang Shiu ,  Hsuan-Ching Chao ,  Kuo-Cyuan Kuo ,  Ming-Kia Chen

IPC: H03D3/24

CPC classification number: H04L7/0331 ,  H04L7/0004

Abstract: A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.

Abstract translation: 电路包括过采样逻辑单元，交流估计器和逻辑处理器。 过采样逻辑单元根据过采样时钟产生多个交流项，并且根据输出时钟从多个交流项输出对应于输出时钟的多个交流项。 交流电估计器在第一预定时间内对从过采样逻辑单元输出的多个交流项执行离散余弦变换和离散正弦变换，以分别产生第一值和第二值。 逻辑处理器在第二预定时间内比较多个第一值和第二值的数量，并且根据比较结果生成时钟数据恢复锁相指示符。

公开(公告)号：US07467313B2

公开(公告)日：2008-12-16

申请号：US11315171

申请日：2005-12-23

Applicant: Chih-Cheng Han ,  Ming-Jiun Chang ,  Hsuan-Ching Chao ,  Chung-Hong Lai

Inventor： Chih-Cheng Han ,  Ming-Jiun Chang ,  Hsuan-Ching Chao ,  Chung-Hong Lai

IPC: G06F1/32

CPC classification number: G06F1/325 ,  G06F1/3203

Abstract: A method for transmitting a power-saving command between a computer system and system chips thereof is described. A power-saving command associated with a first system chip is introduced to the computer system since a BIOS is modified therefore. The CPU of the computer system determines the power mode of the first system chip according to a register therein. As the first system chip enters the power-saving mode, the second system chip is informed entering the power-saving mode as well. Therefore, the peripheral devices coupled to the system chips can enter the power-saving mode smoothly so as to solve that the devices cannot enter the mode simultaneously since there is no power management unit (PMU) installed in the first system chip.

Abstract translation: 描述了在计算机系统及其系统芯片之间发送节电命令的方法。 与第一系统芯片相关联的省电命令被引入到计算机系统，因为BIOS被修改。 计算机系统的CPU根据其中的寄存器来确定第一系统芯片的功率模式。 当第一个系统芯片进入省电模式时，第二个系统芯片也被通知进入省电模式。 因此，耦合到系统芯片的外围设备可以平滑地进入省电模式，以解决设备不能同时进入模式，因为在第一系统芯片中没有安装电源管理单元（PMU）。

公开(公告)号：US07079592B2

公开(公告)日：2006-07-18

申请号：US10170451

申请日：2002-06-14

Applicant: Cheng-Yuan Chang ,  Jie-Hau Huang ,  Hong-Chin Lin ,  Guu-Chang Yang ,  Yung-Hsien Chang ,  Hsuan-Ching Chao

Inventor： Cheng-Yuan Chang ,  Jie-Hau Huang ,  Hong-Chin Lin ,  Guu-Chang Yang ,  Yung-Hsien Chang ,  Hsuan-Ching Chao

IPC: H04L27/22 ,  H04L27/06 ,  H04J11/00

CPC classification number: H04L23/02

Abstract: The present invention relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively. The fast walsh block demodulation device comprises: a plurality of adders (operators) constructed to be a first-level correlation calculation circuit and a second-level correlation calculation circuit, and a plurality of process modules constructed to be a third-level correlation calculation circuit, the process modules having the functions of picking one maximum value from four values and performing third-level correlation calculation of conventional basic fast walsh block demodulation device.

Abstract translation: 本发明涉及一种在接收机处的双级相关计算解调系统和快速沃尔什块解调装置，其中双级相关计算解调系统具有双级相关计算的特征，其中随后的第二 阶段相关计算依赖于第一阶段相关计算结果，通过利用CCK码字中的不完全正交特性来分别排列在第一阶段相关计算中运行的CCK码字和二阶相关计算。 快速沃尔什块解调装置包括：构成为第一级相关计算电路和第二级相关计算电路的多个加法器（运算符），以及构成为第三级相关计算电路的多个处理模块 该处理模块具有从四个值中选出一个最大值并执行常规基本快速沃尔什块解调装置的第三级相关计算的功能。

公开(公告)号：US08566501B2

公开(公告)日：2013-10-22

申请号：US13233008

申请日：2011-09-14

Applicant: Hsuan-Ching Chao ,  Cheng-Pin Huang ,  Yu-Chiun Lin ,  Chia-Chun Chiang

Inventor： Hsuan-Ching Chao ,  Cheng-Pin Huang ,  Yu-Chiun Lin ,  Chia-Chun Chiang

IPC: G06F13/00

CPC classification number: G06F11/221

Abstract: A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus.

Abstract translation: 用于同时分析性能和错误的电路包括映射单元和USB 3.0数据流分析器。 映射单元用于映射通过USB 3.0主机的外围组件互连快速和内部事件传输到USB 3.0主机的命令到USB 3.0总线的数据包。 USB 3.0数据流分析仪用于通过USB 3.0总线的数据包分析USB 3.0主机的性能和错误。

公开(公告)号：US07467308B2

公开(公告)日：2008-12-16

申请号：US11315502

申请日：2005-12-23

Applicant: Ming-Jiun Chang ,  Chih-Cheng Han ,  Hsuan-Ching Chao ,  Chung-Hong Lai

Inventor： Ming-Jiun Chang ,  Chih-Cheng Han ,  Hsuan-Ching Chao ,  Chung-Hong Lai

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/325

Abstract: A PCI-Express bus is incorporated in a method for transmitting a power-saving command between a computer system and its plurality of peripheral devices of the present invention. More particularly, a specific power management command is introduced into the signal transmission protocol of a system command, which is transmitted between the plural system chips. Therefore, the peripheral devices coupled with the system chips can enter a certain power mode simultaneously. The present invention is used to solve the problem of the peripheral devices cannot enter the certain power mode since the system chip has no power management unit disposed under the PCI-Express structure.

Abstract translation: 在本发明的计算机系统与其多个外围设备之间发送功率节省命令的方法中并入有PCI-Express总线。 更具体地，将特定的功率管理命令引入到在多个系统芯片之间传输的系统命令的信号传输协议。 因此，与系统芯片耦合的外围设备可以同时进入一定的功率模式。 本发明用于解决由于系统芯片没有配置在PCI-Express结构下的电源管理单元，外围设备无法进入某种功率模式的问题。

公开(公告)号：US20060236139A1

公开(公告)日：2006-10-19

申请号：US11315502

申请日：2005-12-23

Applicant: Ming-Jiun Chang ,  Chih-Cheng Han ,  Hsuan-Ching Chao ,  Chung-Hong Lai

Inventor： Ming-Jiun Chang ,  Chih-Cheng Han ,  Hsuan-Ching Chao ,  Chung-Hong Lai

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/325

Abstract: A PCI-Express bus is incorporated in a method for transmitting a power-saving command between a computer system and its plurality of peripheral devices of the present invention. More particularly, a specific power management command is introduced into the signal transmission protocol of a system command, which is transmitted between the plural system chips. Therefore, the peripheral devices coupled with the system chips can enter a certain power mode simultaneously. The present invention is used to solve the problem of the peripheral devices cannot enter the certain power mode since the system chip has no power management unit disposed under the PCI-Express structure.

Abstract translation: 在本发明的计算机系统与其多个外围设备之间发送功率节省命令的方法中并入有PCI-Express总线。 更具体地，将特定的功率管理命令引入到在多个系统芯片之间传输的系统命令的信号传输协议。 因此，与系统芯片耦合的外围设备可以同时进入一定的功率模式。 本发明用于解决由于系统芯片没有配置在PCI-Express结构下的电源管理单元，外围设备无法进入某种功率模式的问题。