中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.013 seconds)

    Dynamic hardware multithreading and partitioned hardware multithreading
    3.
    发明授权
    Dynamic hardware multithreading and partitioned hardware multithreading 失效
    动态硬件多线程和分区硬件多线程

    公开(公告)号：US07698540B2

    公开(公告)日：2010-04-13

    申请号：US11591140

    申请日：2006-10-31

    Applicant: Scott J. Norton ,  Thomas L. Vaden ,  James Callister

    Inventor： Scott J. Norton ,  Thomas L. Vaden ,  James Callister

    IPC: G06F9/00

    CPC classification number: G06F9/485

    Abstract: In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.

    Abstract translation: 在本发明的实施例中，一种用于动态硬件多线程的方法包括：在处理器核心中使用硬件停止功能或硬件产出功能，以便启用或禁用共享核心的硬件线程; 其中所述硬件线程通过将所述硬件线程置于停止状态或产出状态而被禁用，并且允许另一硬件线程利用所述核。

    Dynamic hardware multithreading and partitioned hardware multithreading
    4.
    发明申请
    Dynamic hardware multithreading and partitioned hardware multithreading 失效
    动态硬件多线程和分区硬件多线程

    公开(公告)号：US20080114973A1

    公开(公告)日：2008-05-15

    申请号：US11591140

    申请日：2006-10-31

    Applicant: Scott J. Norton ,  Thomas L. Vaden ,  James Callister

    Inventor： Scott J. Norton ,  Thomas L. Vaden ,  James Callister

    IPC: G06F9/44

    CPC classification number: G06F9/485

    Abstract: In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.

    Abstract translation: 在本发明的实施例中，一种用于动态硬件多线程的方法包括：在处理器核心中使用硬件停止功能或硬件产出功能，以便启用或禁用共享核心的硬件线程; 其中所述硬件线程通过将所述硬件线程置于停止状态或产出状态而被禁用，并且允许另一硬件线程利用所述核。

    Acquiring instruction addresses associated with performance monitoring events
    5.
    发明申请
    Acquiring instruction addresses associated with performance monitoring events 失效
    获取与性能监控事件相关的指令地址

    公开(公告)号：US20060224873A1

    公开(公告)日：2006-10-05

    申请号：US11095072

    申请日：2005-03-31

    Applicant: James McCormick ,  James Callister ,  Susith Fernando

    Inventor： James McCormick ,  James Callister ,  Susith Fernando

    IPC: G06F9/44

    CPC classification number: G06F9/3861 ,  G06F11/3476 ,  G06F2201/86

    Abstract: Systems, methodologies, media, and other embodiments associated with acquiring instruction addresses associated with performance monitoring events are described. One exemplary system embodiment includes logic for recording instruction and state data associated with events countable by performance monitoring logic associated with a pipelined processor. The exemplary system embodiment may also include logic for traversing the instruction and state data on a cycle count basis. The exemplary system may also include logic for traversing the instruction and state data on a retirement count basis.

    Abstract translation: 描述与获取与性能监视事件相关联的指令地址相关联的系统，方法，介质和其他实施例。 一个示例性系统实施例包括用于记录与由流水线处理器相关联的性能监视逻辑可计数的事件相关联的指令和状态数据的逻辑。 示例性系统实施例还可以包括用于以循环计数为基础遍历指令和状态数据的逻辑。 示例性系统还可以包括用于在退休计数的基础上遍历指令和状态数据的逻辑。

    MECHANISM TO PROVIDE HIGH PERFORMANCE AND FAIRNESS IN A MULTI-THREADING COMPUTER SYSTEM
    6.
    发明申请
    MECHANISM TO PROVIDE HIGH PERFORMANCE AND FAIRNESS IN A MULTI-THREADING COMPUTER SYSTEM 审中-公开
    在多线程计算机系统中提供高性能和公平性的机制

    公开(公告)号：US20140181484A1

    公开(公告)日：2014-06-26

    申请号：US13725934

    申请日：2012-12-21

    Applicant: James Callister ,  Don Soltis ,  Rohit Bhatia ,  Ramkumar Srinivasan ,  Steven Bostian ,  Richard M. Blumberg

    Inventor： James Callister ,  Don Soltis ,  Rohit Bhatia ,  Ramkumar Srinivasan ,  Steven Bostian ,  Richard M. Blumberg

    IPC: G06F9/38

    CPC classification number: G06F9/3851 ,  G06F9/4881

    Abstract: According to one embodiment, a processor includes an execution pipeline for executing a plurality of threads, including a first thread and a second thread. The processor further includes a multi-thread controller (MTC) coupled to the execution pipeline to determine whether to switch threads between the first and second thread based on a thread switch policy that is selected from a list of thread switch policies based on unfairness levels of the first and second thread, and in response to determining to switch threads, to switch from executing the first thread to executing the second thread.

    Abstract translation: 根据一个实施例，处理器包括用于执行包括第一线程和第二线程的多个线程的执行流水线。 处理器还包括耦合到执行流水线的多线程控制器（MTC），以基于从线程切换策略列表中选择的线程切换策略来确定是否在第一和第二线程之间切换线程，所述线程切换策略基于线程切换策略的列表， 第一线程和第二线程，并且响应于确定切换线程，从执行第一线程切换到执行第二线程。

    Systems and methods for re-ordering instructions
    7.
    发明申请
    Systems and methods for re-ordering instructions 有权
    用于重新排序指令的系统和方法

    公开(公告)号：US20070055961A1

    公开(公告)日：2007-03-08

    申请号：US11209555

    申请日：2005-08-23

    Applicant: James Callister ,  Richard Hank ,  Teresa Johnson

    Inventor： James Callister ,  Richard Hank ,  Teresa Johnson

    IPC: G06F9/45

    CPC classification number: G06F8/445 ,  G06F9/26 ,  G06F9/30043

    Abstract: Systems, methodologies, computer-readable media, and other embodiments associated with ordering instructions are described. One exemplary system embodiment can include an analysis logic configured to analyze executable instructions from an executable program. A re-write logic can be configured to re-order selected load instructions within the executable program based on latency times for the selected load instructions.

    Abstract translation: 描述了与订购指令相关联的系统，方法，计算机可读介质和其他实施例。 一个示例性系统实施例可以包括被配置为从可执行程序分析可执行指令的分析逻辑。 可以将重写逻辑配置为基于所选择的加载指令的延迟时间重新排序可执行程序内的所选加载指令。

    Mitigating context switch cache miss penalty
    8.
    发明申请
    Mitigating context switch cache miss penalty 有权
    减轻上下文切换缓存未命中

    公开(公告)号：US20070067602A1

    公开(公告)日：2007-03-22

    申请号：US11228058

    申请日：2005-09-16

    Applicant: James Callister ,  Eric Delano ,  Rohit Bhatia ,  Shawn Walker ,  Mark Gibson

    Inventor： James Callister ,  Eric Delano ,  Rohit Bhatia ,  Shawn Walker ,  Mark Gibson

    IPC: G06F12/00

    CPC classification number: G06F12/1027 ,  G06F12/0842

    Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.

    Abstract translation: 描述了与减轻上下文切换高速缓存和TLB未命中的影响相关联的系统，方法，媒体和其他实施例。 一个示例性系统实施例包括被配置为运行多处理虚拟存储器操作系统的处理器。 处理器可以可操作地连接到存储器，并且可以包括被配置为存储TLB条目的高速缓存和翻译后备缓冲器（TLB）。 示例性系统可以包括上下文控制逻辑，其被配置为选择性地将数据从TLB复制到数据存储器，用于从处理器交换出的第一进程，并且将数据从数据存储选择性地复制到TLB，以将第二进程交换到 到处理器。

Patent Agency Ranking