公开(公告)号：US20050099851A1

公开(公告)日：2005-05-12

申请号：US10703017

申请日：2003-11-06

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： G11C7/10 ,  G11C8/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1012 ,  G11C7/1051 ,  G11C8/10

摘要： A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.

摘要翻译： 位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。 各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。 选择器处于耦合到相应输出节点的Q组中。 每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。 第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。 第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。 用于N + 1个多路复用器的输出逻辑门分别​​具有分别耦合到R个节点的R个输入。 多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。

公开(公告)号：US20070229132A1

公开(公告)日：2007-10-04

申请号：US11277691

申请日：2006-03-28

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： H03K3/00

CPC分类号： H03K3/0375 ,  G01R31/318533 ,  G01R31/318536 ,  H03K3/013 ,  H03K3/356121 ,  H03K19/00392

摘要： A latch is described that provides soft error rate protection with integrated scan capability and collision avoidance. The latch has a latch output node and a first, second, and third sublatches. Each sublatch has a respective input circuitry, output node, and feedback circuitry coupled to the output node for reinforcing an output signal of the sublatch. Each sublatch is operable to receive a data signal at its input circuitry and responsively generate a binary-state output signal on its output nodes. The first and second output nodes such that, if an output of the third sublatch changes, the first and second sublatches force the third sublatch to have a same output. This “forced” change reduces the soft error rate in the latch and the output signal of the latch output node is restored without the sublatches colliding.

摘要翻译： 描述了提供具有集成扫描能力和避免碰撞的软错误率保护的锁存器。 闩锁具有闩锁输出节点和第一，第二和第三子实体。 每个分支具有相应的输入电路，输出节点和耦合到输出节点的反馈电路，用于加强子锁的输出信号。 每个子选项可操作以在其输入电路处接收数据信号，并在其输出节点上响应地生成二进制状态输出信号。 第一和第二输出节点使得如果第三个分支的输出发生变化，则第一和第二个分页强制第三个分块具有相同的输出。 这种“强制”改变降低了锁存器中的软错误率，并且恢复锁存器输出节点的输出信号，而不会使得副本碰撞。

公开(公告)号：US20060181909A1

公开(公告)日：2006-08-17

申请号：US11055803

申请日：2005-02-11

申请人： Joaquin Hinojosa ,  Eric Fluhr ,  Michael Lee ,  Jose Paredes ,  Ed Seewann

发明人： Joaquin Hinojosa ,  Eric Fluhr ,  Michael Lee ,  Jose Paredes ,  Ed Seewann

IPC分类号： G11C15/00

CPC分类号： G06F12/1027 ,  G06F2212/652 ,  G11C15/00

摘要： A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.

摘要翻译： 公开了一种CAM系统，其中将地址转换请求作为输入搜索数据提供给动态比较位线发生器。 动态比较位线发生器还接收比较掩码，并以比特的形式将比较掩码应用于相关的输入搜索数据位。 掩码包含指定所选页面大小的信息和可应用于进行指定搜索的比较数组的选定逻辑模式。 比较数组耦合到比较数组指示搜索结果的数据阵列。

公开(公告)号：US20060039203A1

公开(公告)日：2006-02-23

申请号：US10922247

申请日：2004-08-19

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： G11C7/10

CPC分类号： G11C7/22

摘要： A register file apparatus and method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

摘要翻译： 使用检测单元结合读写后阻塞的寄存器文件装置和方法在高性能寄存器文件中提供改进的读访问时间。 一个或多个与寄存器文件单元相同并且位于寄存器文件阵列中的检测单元用于通过将检测单元配置为在写入时的交替值或在写入之后变为特定值来控制寄存器文件中的读取操作 然后通过检测有源检测单元的状态变化来检测写入是否已经完成。 状态改变检测可以用于延迟读选通脉冲的前沿，或者可以在访问控制逻辑中使用以延迟下一个读选通脉冲的产生。 寄存器文件因此提供了一种可扩展的设计，不需要针对每个应用进行调整，并且跟踪过电压和时钟偏移变化。

公开(公告)号：US20060179346A1

公开(公告)日：2006-08-10

申请号：US11054988

申请日：2005-02-10

申请人： James Bishop ,  Hung Le ,  Michael Mack ,  Jafar Nahidi ,  Dung Nguyen ,  Jose Paredes ,  Scott Swaney ,  Brian Thompto

发明人： James Bishop ,  Hung Le ,  Michael Mack ,  Jafar Nahidi ,  Dung Nguyen ,  Jose Paredes ,  Scott Swaney ,  Brian Thompto

IPC分类号： G06F11/00

CPC分类号： G06F11/1407

摘要： A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

公开(公告)号：US20060179207A1

公开(公告)日：2006-08-10

申请号：US11055258

申请日：2005-02-10

申请人： Susan Eisen ,  Hung Le ,  Michael Mack ,  Dung Nguyen ,  Jose Paredes ,  Scott Swaney

发明人： Susan Eisen ,  Hung Le ,  Michael Mack ,  Dung Nguyen ,  Jose Paredes ,  Scott Swaney

IPC分类号： G06F12/14

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US20050216698A1

公开(公告)日：2005-09-29

申请号：US10798902

申请日：2004-03-11

申请人： Sam Chu ,  Saiful Islam ,  Shelton Leung ,  Jose Paredes

发明人： Sam Chu ,  Saiful Islam ,  Shelton Leung ,  Jose Paredes

IPC分类号： G06F9/30 ,  G06F15/00

CPC分类号： G06F9/30141

摘要： A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

摘要翻译： 集成电路中经常使用寄存器文件来临时保存数据。 有时，这些数据需要在寄存器文件中保留一段时间，例如当有停机操作时。 传统的寄存器文件已经使用保持多路复用器来执行这种失速操作。 然而，多路复用器插入在高性能集成电路中不期望的延迟。 多路复用器被替换为耦合到寄存器堆的全局位线的三态反相器，这使得从寄存器文件数据访问时间的这个附加延迟最小化。

公开(公告)号：US20070171757A1

公开(公告)日：2007-07-26

申请号：US11340535

申请日：2006-01-26

申请人： Michael Lee ,  Jose Paredes ,  Peter Klim ,  Sam Chu

发明人： Michael Lee ,  Jose Paredes ,  Peter Klim ,  Sam Chu

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

摘要翻译： 一种基于写入数据的选择性行激励的系统和方法，具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联，并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及M位行驱动器装置116，响应于M行104中的每一个的均匀字数据位，以禁止均匀字数据位为第一值的M行104的通电。

公开(公告)号：US20060038588A1

公开(公告)日：2006-02-23

申请号：US10922271

申请日：2004-08-19

申请人： Sam Chu ,  Peter Klim ,  Michael Hyeok Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Hyeok Lee ,  Jose Paredes

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation provides a compact circuit for blocking the indication of a non-evaluated state of a dynamic logic gate until a control signal has ended. The control signal is connected to a precharge input of the control element and a summing node is connected to one or more evaluation trees and to the control element output via an inverter. The inverter is connected to an override circuit that forces the output of the control element to a state opposite the precharge state until the control signal has ended. The output of the control element then assumes a state corresponding to the precharge state until an evaluation occurs. The control element output thus produces a window signal indicating the interval between the end of the control signal and the evaluation.

摘要翻译： 用于发信号通知控制信号的结束与逻辑评估之间的间隔的动态静态逻辑控制元件提供紧凑的电路，用于阻止动态逻辑门的未评估状态的指示，直到控制信号结束为止。 控制信号连接到控制元件的预充电输入，并且求和节点经由逆变器连接到一个或多个评估树和控制元件输出。 逆变器连接到超控电路，其将控制元件的输出强制到与预充电状态相反的状态，直到控制信号结束。 然后，控制元件的输出呈现与预充电状态相对应的状态，直到评估发生。 因此，控制元件输出产生指示控制信号的结束与评估之间的间隔的窗口信号。

公开(公告)号：US20060184852A1

公开(公告)日：2006-08-17

申请号：US11050351

申请日：2005-02-03

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： H04L1/00 ,  H03M13/00 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30

CPC分类号： G06F11/24

摘要： A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.