公开(公告)号：US20060181909A1

公开(公告)日：2006-08-17

申请号：US11055803

申请日：2005-02-11

申请人： Joaquin Hinojosa ,  Eric Fluhr ,  Michael Lee ,  Jose Paredes ,  Ed Seewann

发明人： Joaquin Hinojosa ,  Eric Fluhr ,  Michael Lee ,  Jose Paredes ,  Ed Seewann

IPC分类号： G11C15/00

CPC分类号： G06F12/1027 ,  G06F2212/652 ,  G11C15/00

摘要： A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.

摘要翻译： 公开了一种CAM系统，其中将地址转换请求作为输入搜索数据提供给动态比较位线发生器。 动态比较位线发生器还接收比较掩码，并以比特的形式将比较掩码应用于相关的输入搜索数据位。 掩码包含指定所选页面大小的信息和可应用于进行指定搜索的比较数组的选定逻辑模式。 比较数组耦合到比较数组指示搜索结果的数据阵列。

公开(公告)号：US20060181908A1

公开(公告)日：2006-08-17

申请号：US11055802

申请日：2005-02-11

申请人： Yuen Chan ,  Masood Khan ,  Michael Lee ,  Ed Seewann

发明人： Yuen Chan ,  Masood Khan ,  Michael Lee ,  Ed Seewann

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： A CAM system is disclosed in which compare data, for example an address translation request, is provided as input search data to a search line generator. The search line generator presents search line input data, through a buffer, to CAM and RAM array systems that include dynamically precharged and evaluated memory cells. Timing sequences in the CAM system are controlled by a series of individually triggered one shot pulse generators. The one shot pulse generators control the timing of CAM system activities, for example the precharge of CAM subsystems, so that these activities are staggered in time. This timing approach improves power consumption and evaluation time within the CAM system. By distributing precharging activities in time throughout the CAM cycle, current peaking during the CAM cycle is reduced. The CAM system latches results in an output latch that is controlled by a one shot pulse generator.

摘要翻译： 公开了一种CAM系统，其中将比较数据（例如地址转换请求）作为输入搜索数据提供给搜索线发生器。 搜索线生成器通过缓冲器将搜索线输入数据呈现给包括动态预充电和评估的存储器单元的CAM和RAM阵列系统。 CAM系统中的定时序列由一系列单独触发的单脉冲发生器控制。 单脉冲发生器控制CAM系统活动的时间，例如CAM子系统的预充电，以便这些活动及时交错。 该定时方法提高了CAM系统的功耗和评估时间。 通过在整个CAM循环中及时分配预充电活动，CAM循环期间的当前峰值降低。 CAM系统锁存器产生由单触发脉冲发生器控制的输出锁存器。

公开(公告)号：US20070229132A1

公开(公告)日：2007-10-04

申请号：US11277691

申请日：2006-03-28

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： H03K3/00

CPC分类号： H03K3/0375 ,  G01R31/318533 ,  G01R31/318536 ,  H03K3/013 ,  H03K3/356121 ,  H03K19/00392

摘要： A latch is described that provides soft error rate protection with integrated scan capability and collision avoidance. The latch has a latch output node and a first, second, and third sublatches. Each sublatch has a respective input circuitry, output node, and feedback circuitry coupled to the output node for reinforcing an output signal of the sublatch. Each sublatch is operable to receive a data signal at its input circuitry and responsively generate a binary-state output signal on its output nodes. The first and second output nodes such that, if an output of the third sublatch changes, the first and second sublatches force the third sublatch to have a same output. This “forced” change reduces the soft error rate in the latch and the output signal of the latch output node is restored without the sublatches colliding.

摘要翻译： 描述了提供具有集成扫描能力和避免碰撞的软错误率保护的锁存器。 闩锁具有闩锁输出节点和第一，第二和第三子实体。 每个分支具有相应的输入电路，输出节点和耦合到输出节点的反馈电路，用于加强子锁的输出信号。 每个子选项可操作以在其输入电路处接收数据信号，并在其输出节点上响应地生成二进制状态输出信号。 第一和第二输出节点使得如果第三个分支的输出发生变化，则第一和第二个分页强制第三个分块具有相同的输出。 这种“强制”改变降低了锁存器中的软错误率，并且恢复锁存器输出节点的输出信号，而不会使得副本碰撞。

公开(公告)号：US20060039203A1

公开(公告)日：2006-02-23

申请号：US10922247

申请日：2004-08-19

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： G11C7/10

CPC分类号： G11C7/22

摘要： A register file apparatus and method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

摘要翻译： 使用检测单元结合读写后阻塞的寄存器文件装置和方法在高性能寄存器文件中提供改进的读访问时间。 一个或多个与寄存器文件单元相同并且位于寄存器文件阵列中的检测单元用于通过将检测单元配置为在写入时的交替值或在写入之后变为特定值来控制寄存器文件中的读取操作 然后通过检测有源检测单元的状态变化来检测写入是否已经完成。 状态改变检测可以用于延迟读选通脉冲的前沿，或者可以在访问控制逻辑中使用以延迟下一个读选通脉冲的产生。 寄存器文件因此提供了一种可扩展的设计，不需要针对每个应用进行调整，并且跟踪过电压和时钟偏移变化。

公开(公告)号：US20060184852A1

公开(公告)日：2006-08-17

申请号：US11050351

申请日：2005-02-03

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： H04L1/00 ,  H03M13/00 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30

CPC分类号： G06F11/24

摘要： A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.

公开(公告)号：US20050099205A1

公开(公告)日：2005-05-12

申请号：US10703016

申请日：2003-11-06

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： G06F7/38 ,  G11C7/10 ,  H03K19/0175 ,  H03K19/173

CPC分类号： G11C7/1048 ,  G11C2207/007

摘要： A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.

摘要翻译： 寄存器 - 文件位读取装置包括：解码器，可操作用于接收多个地址位信号，并响应地在M个选择行之一中断言选择信号。 每个选择行对应于M个寄存器文件单元中的相应一个。 该装置还包括具有Q个输出节点和M个选择器的多路复用器。 每个选择器耦合到选择线之一，并选择线对应的寄存器文件单元。 选择器处于Q组中，每组耦合到多路复用器的输出节点中的相应一个。 该装置还包括具有Q输入的输出逻辑门，耦合到多路复用器输出节点中的相应一个。 多路复用器包括Q个上拉，其中每个Q上拉耦合到多路复用器输出节点中的相应一个，并且可操作以响应于地址位信号之一驱动其多路复用器输出节点。

公开(公告)号：US20050099851A1

公开(公告)日：2005-05-12

申请号：US10703017

申请日：2003-11-06

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： G11C7/10 ,  G11C8/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1012 ,  G11C7/1051 ,  G11C8/10

摘要： A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.

摘要翻译： 位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。 各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。 选择器处于耦合到相应输出节点的Q组中。 每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。 第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。 第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。 用于N + 1个多路复用器的输出逻辑门分别​​具有分别耦合到R个节点的R个输入。 多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。

公开(公告)号：US20070171757A1

公开(公告)日：2007-07-26

申请号：US11340535

申请日：2006-01-26

申请人： Michael Lee ,  Jose Paredes ,  Peter Klim ,  Sam Chu

发明人： Michael Lee ,  Jose Paredes ,  Peter Klim ,  Sam Chu

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

摘要翻译： 一种基于写入数据的选择性行激励的系统和方法，具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联，并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及M位行驱动器装置116，响应于M行104中的每一个的均匀字数据位，以禁止均匀字数据位为第一值的M行104的通电。

公开(公告)号：US20200263402A1

公开(公告)日：2020-08-20

申请号：US16869046

申请日：2020-05-07

申请人： Michael Lee

发明人： Michael Lee

IPC分类号： E03C1/308

摘要： An automatic toilet plunger for clearing a blockage in a toilet includes a pipe having a plunger head engaged to a bottom end thereof so that the plunger head is in fluidic communication with the pipe. A pair of arms is hingedly engaged to the pipe. The arms are selectively positionable in an extended configuration and a stowed configuration. In the extended configuration, the arms engage a seat of a toilet. The arms fold downwardly, toward the bottom end of the pipe, into the stowed configuration. A handle, which is engaged to a top end of the pipe and which extends bilaterally therefrom, is hollow and in fluidic communication with the pipe. An actuator is engaged to at least one of the handle and the pipe and positioned therein. The actuator is manipulated to cause the plunger head to clear a blockage in the toilet.

公开(公告)号：US10655312B1

公开(公告)日：2020-05-19

申请号：US16184128

申请日：2018-11-08

申请人： Michael Lee

发明人： Michael Lee

IPC分类号： E03C1/308

摘要： An automatic toilet plunger includes a plunger body having a top end, a bottom end, and an inside. The plunger body is hollow and cylindrical. A plunger head is coupled to the bottom end of the plunger body. A plunging mechanism is coupled inside the plunger body of the plunger. The plunging mechanism is in operational communication with the plunger head and is configured to cause the plunger head to clear a toilet. A plurality of controls is coupled to the plunger body and is in operational communication with the plunging mechanism. A power source is coupled to the plunger body and is in operational communication with, and provides power to, the plunging mechanism.