公开(公告)号：US20060184852A1

公开(公告)日：2006-08-17

申请号：US11050351

申请日：2005-02-03

Applicant: Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

Inventor： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC: H04L1/00 ,  H03M13/00 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30

CPC classification number: G06F11/24

Abstract: A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.

公开(公告)号：US20060179257A1

公开(公告)日：2006-08-10

申请号：US11054276

申请日：2005-02-09

Applicant: Sam Chu ,  Maureen Delaney ,  Saiful Islam ,  Dung Nguyen ,  Jafar Nahidi

Inventor： Sam Chu ,  Maureen Delaney ,  Saiful Islam ,  Dung Nguyen ,  Jafar Nahidi

IPC: G06F12/00

CPC classification number: G06F9/30141

Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.

Abstract translation: 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。

公开(公告)号：US20060171208A1

公开(公告)日：2006-08-03

申请号：US11044449

申请日：2005-01-27

Applicant: Sam Chu ,  Maureen Delaney ,  Saiful Islam ,  Jafar Nahidi ,  Dung Nguyen

Inventor： Sam Chu ,  Maureen Delaney ,  Saiful Islam ,  Jafar Nahidi ,  Dung Nguyen

IPC: G11C7/10

CPC classification number: G06F9/30141 ,  G06F9/30098

Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.

Abstract translation: 提供了一种用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法。 利用该装置和方法，从电路配置中消除了常规寄存器文件系统中的2：1多路复用器，而是提供了一半地址的附加主复用器，例如寄存器堆的前四个子阵列， 需要包装能力。 这些附加的主多路复用器接收读地址和移位的读字线信号。 另一个主复用器接收读地址和未移位的读字线信号。 来自移位和未移位的主复用器的输出被提供给一组次级多路复用器，它们将来自移位和未移位的主复用器的输出的比特复用以产生要由多个读/写寄存器堆使用的读地址 系统。

公开(公告)号：US20050099205A1

公开(公告)日：2005-05-12

申请号：US10703016

申请日：2003-11-06

Applicant: Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

Inventor： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC: G06F7/38 ,  G11C7/10 ,  H03K19/0175 ,  H03K19/173

CPC classification number: G11C7/1048 ,  G11C2207/007

Abstract: A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.

Abstract translation: 寄存器 - 文件位读取装置包括：解码器，可操作用于接收多个地址位信号，并响应地在M个选择行之一中断言选择信号。 每个选择行对应于M个寄存器文件单元中的相应一个。 该装置还包括具有Q个输出节点和M个选择器的多路复用器。 每个选择器耦合到选择线之一，并选择线对应的寄存器文件单元。 选择器处于Q组中，每组耦合到多路复用器的输出节点中的相应一个。 该装置还包括具有Q输入的输出逻辑门，耦合到多路复用器输出节点中的相应一个。 多路复用器包括Q个上拉，其中每个Q上拉耦合到多路复用器输出节点中的相应一个，并且可操作以响应于地址位信号之一驱动其多路复用器输出节点。

公开(公告)号：US5783471A

公开(公告)日：1998-07-21

申请号：US336819

申请日：1994-11-09

Applicant: Sam Chu

Inventor： Sam Chu

IPC: H01L21/8242 ,  H01L21/8247 ,  H01L29/45

CPC classification number: H01L27/11526 ,  H01L27/10844 ,  H01L27/11546 ,  H01L29/456 ,  Y10S257/905

Abstract: A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of self-aligned memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation. In this manner, the self-formed contact allows for significant size reduction of the contact pitch. Moreover, using other plugs to form the self-aligned source lines of the array further reduces the size of the word line pitch, thereby dramatically reducing the associated cell size and allowing formation of ultra-high density memory arrays. Additionally, other metal self-aligned source significantly reduces source line resistance, thereby eliminating the need for frequent source line contacts, increasing cell efficiency and improving cell performance.

Abstract translation: 提供了一种结构和方法，其通过在阵列中形成自形成接触和自对准源极线来减小存储单元尺寸。 在本发明的一个实施例中，阵列中形成多个自对准存储单元。 然后，将第一绝缘层沉积在阵列上，随后蚀刻以在每个存储单元的侧壁上形成间隔物。 然后在相邻间隔件之间形成导电塞。 随后，在阵列上沉积第二绝缘层。 最后，通过第二绝缘层形成第一组插头的漏极接触。 其他插头形成阵列的源线。 因为本发明提供自形成的接触，所以仅蚀刻第二绝缘层以建立金属位线与下面的扩散漏极区之间的接触。 因此，本发明确保每个存储单元的适当隔离，同时减少接触形成所需的面积。 以这种方式，自形成接触允许接触间距的显着尺寸减小。 此外，使用其他插头来形成阵列的自对准源极线进一步减小了字线间距的大小，从而显着地减小了相关的单元尺寸并允许形成超高密度存储器阵列。 此外，其他金属自对准源显着降低了源极线电阻，从而消除了频繁的源极线接触的需要，提高电池效率和改善电池性能。

公开(公告)号：US20070229132A1

公开(公告)日：2007-10-04

申请号：US11277691

申请日：2006-03-28

Applicant: Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

Inventor： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC: H03K3/00

CPC classification number: H03K3/0375 ,  G01R31/318533 ,  G01R31/318536 ,  H03K3/013 ,  H03K3/356121 ,  H03K19/00392

Abstract: A latch is described that provides soft error rate protection with integrated scan capability and collision avoidance. The latch has a latch output node and a first, second, and third sublatches. Each sublatch has a respective input circuitry, output node, and feedback circuitry coupled to the output node for reinforcing an output signal of the sublatch. Each sublatch is operable to receive a data signal at its input circuitry and responsively generate a binary-state output signal on its output nodes. The first and second output nodes such that, if an output of the third sublatch changes, the first and second sublatches force the third sublatch to have a same output. This “forced” change reduces the soft error rate in the latch and the output signal of the latch output node is restored without the sublatches colliding.

Abstract translation: 描述了提供具有集成扫描能力和避免碰撞的软错误率保护的锁存器。 闩锁具有闩锁输出节点和第一，第二和第三子实体。 每个分支具有相应的输入电路，输出节点和耦合到输出节点的反馈电路，用于加强子锁的输出信号。 每个子选项可操作以在其输入电路处接收数据信号，并在其输出节点上响应地生成二进制状态输出信号。 第一和第二输出节点使得如果第三个分支的输出发生变化，则第一和第二个分页强制第三个分块具有相同的输出。 这种“强制”改变降低了锁存器中的软错误率，并且恢复锁存器输出节点的输出信号，而不会使得副本碰撞。

公开(公告)号：US20060039203A1

公开(公告)日：2006-02-23

申请号：US10922247

申请日：2004-08-19

Applicant: Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

Inventor： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC: G11C7/10

CPC classification number: G11C7/22

Abstract: A register file apparatus and method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

Abstract translation: 使用检测单元结合读写后阻塞的寄存器文件装置和方法在高性能寄存器文件中提供改进的读访问时间。 一个或多个与寄存器文件单元相同并且位于寄存器文件阵列中的检测单元用于通过将检测单元配置为在写入时的交替值或在写入之后变为特定值来控制寄存器文件中的读取操作 然后通过检测有源检测单元的状态变化来检测写入是否已经完成。 状态改变检测可以用于延迟读选通脉冲的前沿，或者可以在访问控制逻辑中使用以延迟下一个读选通脉冲的产生。 寄存器文件因此提供了一种可扩展的设计，不需要针对每个应用进行调整，并且跟踪过电压和时钟偏移变化。

公开(公告)号：US20050099851A1

公开(公告)日：2005-05-12

申请号：US10703017

申请日：2003-11-06

Applicant: Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

Inventor： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC: G11C7/10 ,  G11C8/10 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1012 ,  G11C7/1051 ,  G11C8/10

Abstract: A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.

Abstract translation: 位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。 各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。 选择器处于耦合到相应输出节点的Q组中。 每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。 第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。 第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。 用于N + 1个多路复用器的输出逻辑门分别​​具有分别耦合到R个节点的R个输入。 多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。

公开(公告)号：US07920592B2

公开(公告)日：2011-04-05

申请号：US11642238

申请日：2006-12-20

Applicant: Chia Sheng Lu ,  Sam Chu

Inventor： Chia Sheng Lu ,  Sam Chu

IPC: H04J3/16 ,  H04J3/18

CPC classification number: H04L47/522 ,  H04L47/24 ,  H04L47/50 ,  H04L47/527

Abstract: A method of bandwidth control and a corresponding bandwidth control device are disclosed, in which a plurality of queues are provided, bandwidth is assigned to each of the queues on the basis of a strict priority scheme, and additional bandwidth is assigned to the queues on the basis of a fair queuing scheme.

Abstract translation: 公开了一种带宽控制方法和相应的带宽控制装置，其中提供多个队列，基于严格优先级方案，将带宽分配给每个队列，并且将附加带宽分配给队列 公平排队计划的基础。

公开(公告)号：US20050216698A1

公开(公告)日：2005-09-29

申请号：US10798902

申请日：2004-03-11

Applicant: Sam Chu ,  Saiful Islam ,  Shelton Leung ,  Jose Paredes

Inventor： Sam Chu ,  Saiful Islam ,  Shelton Leung ,  Jose Paredes

IPC: G06F9/30 ,  G06F15/00

CPC classification number: G06F9/30141

Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

Abstract translation: 集成电路中经常使用寄存器文件来临时保存数据。 有时，这些数据需要在寄存器文件中保留一段时间，例如当有停机操作时。 传统的寄存器文件已经使用保持多路复用器来执行这种失速操作。 然而，多路复用器插入在高性能集成电路中不期望的延迟。 多路复用器被替换为耦合到寄存器堆的全局位线的三态反相器，这使得从寄存器文件数据访问时间的这个附加延迟最小化。