公开(公告)号：US08711073B2

公开(公告)日：2014-04-29

申请号：US12175961

申请日：2008-07-18

Applicant: Min Cheol Lee ,  Seung Hwan Moon

Inventor： Min Cheol Lee ,  Seung Hwan Moon

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2310/0205

Abstract: A display system includes a display panel having a plurality of pixel units, each of the pixel units having first and second divided pixel parts; a first driver for applying a first gate signal to the first divided pixel part; and a second driver for applying a second gate signal to the second divided pixel part, wherein the first and second drivers are integrally formed in the display panel and apply the first and second gate signals to be at least partially time-overlapped through independent driving.

Abstract translation: 显示系统包括具有多个像素单元的显示面板，每个像素单元具有第一和第二分割像素部分; 用于将第一栅极信号施加到第一分割像素部分的第一驱动器; 以及第二驱动器，用于将第二栅极信号施加到第二分割像素部分，其中第一和第二驱动器一体地形成在显示面板中，并且通过独立驱动将第一和第二栅极信号施加至少部分时间重叠。

公开(公告)号：US08400390B2

公开(公告)日：2013-03-19

申请号：US12645902

申请日：2009-12-23

Applicant: Min-Cheol Lee ,  Seung-Hwan Moon

Inventor： Min-Cheol Lee ,  Seung-Hwan Moon

IPC: G09G3/36 ,  G06F3/038 ,  G09G5/00

CPC classification number: G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving device includes a plurality of stages, a first dummy stage connected to the plurality of stages and a second dummy stage connected to the first dummy stage. Stages of the plurality of stages are cascaded. The first dummy stage includes a first charge unit which receives a first input signal from a previous stage of the plurality of stages and is thereby charged, and a first pull-up transistor which outputs a clock signal when the first charge unit reaches a first charge level. The second dummy stage includes a second charge unit which receives a second input signal from the first dummy stage and is thereby charged, and a second pull-up transistor which outputs the clock signal when the second charge unit reaches a second charge level higher than the first charge level.

Abstract translation: 栅极驱动装置包括多个级，连接到多个级的第一虚拟级和连接到第一虚拟级的第二虚拟级。 多级的阶段是级联的。 第一虚拟级包括第一充电单元，其接收来自多级的前一级的第一输入信号并由此充电;以及第一上拉晶体管，其在第一充电单元达到第一充电时输出时钟信号 水平。 第二虚拟级包括第二充电单元，其从第一虚拟级接收第二输入信号并由此被充电;以及第二上拉晶体管，当第二充电单元达到比第二充电电平高的第二充电电平时，输出时钟信号 第一充电水平。

公开(公告)号：US20120311720A1

公开(公告)日：2012-12-06

申请号：US13512527

申请日：2010-11-25

Applicant: Min-cheol Lee ,  Jae-won Choi ,  Dong-sung Kim ,  Jong-shin Kim ,  Nam-geol Lee

Inventor： Min-cheol Lee ,  Jae-won Choi ,  Dong-sung Kim ,  Jong-shin Kim ,  Nam-geol Lee

IPC: G06F21/00

CPC classification number: G06F21/121 ,  A61L2/10 ,  E03C1/06 ,  H04L9/08 ,  H04L9/0866 ,  H04L2209/56 ,  H04L2209/603

Abstract: An application protection method and an application execution method using the same are provided. The application protection method generates a key needed to execute the application which is provided to a user terminal using information on the user terminal, information on the application, and a part of text; and transmits the generated key to the user terminal. Therefore, the application is executed on the device which has a legal right for the application, thereby preventing the illegal use of the application.

Abstract translation: 提供了一种应用保护方法和使用该方法的应用执行方法。 应用保护方法生成使用关于用户终端的信息，应用信息和文本的一部分来提供给用户终端的应用执行所需的密钥; 并将生成的密钥发送到用户终端。 因此，在具有应用的合法权利的设备上执行应用，从而防止应用的非法使用。

公开(公告)号：US08305323B2

公开(公告)日：2012-11-06

申请号：US11960131

申请日：2007-12-19

Applicant: Min-Cheol Lee ,  Byeong-Jae Ahn ,  Jong-Hwan Lee ,  Yeon-Kyu Moon ,  Jong-Hyuk Lee

Inventor： Min-Cheol Lee ,  Byeong-Jae Ahn ,  Jong-Hwan Lee ,  Yeon-Kyu Moon ,  Jong-Hyuk Lee

IPC: G09G3/36 ,  G09G5/00 ,  G06F3/038 ,  H03K23/00 ,  H03K25/00 ,  H03K3/00

CPC classification number: G09G3/3674 ,  G09G2310/0286 ,  G11C19/182

Abstract: A display apparatus includes a gate driver which sequentially outputs a gate signal at a high state in response to a gate control signal and a data driver which converts image data into a data signal in response to a data control signal. The display apparatus further includes a display panel which includes a plurality of gate lines which sequentially receive the gate signal, a plurality of data lines which receive the data signal and a plurality of pixels connected to the gate and data lines and which receive the data signal in response to the gate signal to display an image. The polarity of the data signal is inverted after the gate signal transitions to a low state.

Abstract translation: 显示装置包括：栅极驱动器，其响应于栅极控制信号顺序地输出处于高状态的栅极信号;以及数据驱动器，其响应于数据控制信号将图像数据转换为数据信号。 显示装置还包括显示面板，其包括顺序地接收栅极信号的多个栅极线，接收数据信号的多个数据线和连接到栅极和数据线的多个像素，并且接收数据信号 响应于门信号显示图像。 在门信号转换到低电平状态之后，数据信号的极性反转。

公开(公告)号：US08248550B2

公开(公告)日：2012-08-21

申请号：US12603529

申请日：2009-10-21

Applicant: Min-cheol Lee

Inventor： Min-cheol Lee

IPC: G02F1/136 ,  G02F1/1343 ,  G02F1/1345

CPC classification number: G02F1/1393 ,  G02F1/136213 ,  G09G3/3648 ,  G09G2320/0219 ,  G09G2320/0223

Abstract: A liquid crystal display device includes a first substrate which comprises a plurality of pixels where a thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed, the first substrate including a gate line and a data line which insulatingly intersect each other; and a gate driver which applies a gate driving signal to the gate line, the thin film transistor including a gate electrode which is connected to the gate line; a source electrode which is connected to the data line; and a drain electrode which is connected to the pixel electrode, and the pixels being decreased in a value of Cp/(Cp+Clc+Cst) as going toward the gate driver (where, Cp: a sum of parasitic capacity between the gate electrode and the source electrode and parasitic capacity between the gate electrode and the drain electrode, Clc: liquid crystal capacity, and Cst: storage capacity).

Abstract translation: 液晶显示装置包括：第一基板，其包括形成薄膜晶体管和与薄膜晶体管电连接的像素电极的多个像素，第一基板包括栅极线和彼此绝缘地相交的数据线 ; 以及栅极驱动器，其对栅极线施加栅极驱动信号，所述薄膜晶体管包括连接到所述栅极线的栅电极; 连接到数据线的源电极; 以及连接到像素电极的漏电极，并且像素朝向栅极驱动器的Cp /（Cp + Clc + Cst）值减小（其中，Cp：栅电极之间的寄生电容之和 源电极和栅电极与漏电极之间的寄生电容，Clc：液晶容量，Cst：存储容量）。

公开(公告)号：US20110205462A1

公开(公告)日：2011-08-25

申请号：US13097579

申请日：2011-04-29

Applicant: Min-Cheol LEE

Inventor： Min-Cheol LEE

IPC: G02F1/1343

CPC classification number: G09G3/3659 ,  G02F1/136213 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2300/0443 ,  G09G2320/028

Abstract: A liquid crystal display includes a first gate electrode, a storage electrode having a body and an extension, a first semiconductor formed on a gate insulating layer, a first drain electrode formed on the first semiconductor, separated from a first source electrode, and having an end portion overlapping the first gate electrode, and an expansion overlapping the body of the storage electrode and distanced from the end portion with a connection connecting the end portion and the expansion and overlapping the extension of the storage electrode, a passivation layer having a contact hole exposing the expansion of the first drain electrode, and a first field-generating electrode connected to the first drain electrode through the contact hole.

Abstract translation: 液晶显示器包括第一栅电极，具有本体和延伸部的存储电极，形成在栅极绝缘层上的第一半导体，形成在第一半导体上的第一漏电极，与第一源电极分离，并且具有 端部与第一栅电极重叠，并且膨胀与存储电极的主体重叠并且与端部间隔开，连接端部和扩展部并且与存储电极的延伸部重叠;钝化层，具有接触孔 暴露第一漏电极的膨胀，以及通过接触孔连接到第一漏电极的第一场产生电极。

公开(公告)号：US20100156869A1

公开(公告)日：2010-06-24

申请号：US12645902

申请日：2009-12-23

Applicant: Min-Cheol LEE ,  Seung-Hwan MOON

Inventor： Min-Cheol LEE ,  Seung-Hwan MOON

IPC: G09G3/36 ,  H03B1/00 ,  G09G5/00

CPC classification number: G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving device includes a plurality of stages, a first dummy stage connected to the plurality of stages and a second dummy stage connected to the first dummy stage. Stages of the plurality of stages are cascaded. The first dummy stage includes a first charge unit which receives a first input signal from a previous stage of the plurality of stages and is thereby charged, and a first pull-up transistor which outputs a clock signal when the first charge unit reaches a first charge level. The second dummy stage includes a second charge unit which receives a second input signal from the first dummy stage and is thereby charged, and a second pull-up transistor which outputs the clock signal when the second charge unit reaches a second charge level higher than the first charge level.

Abstract translation: 栅极驱动装置包括多个级，连接到多个级的第一虚拟级和连接到第一虚拟级的第二虚拟级。 多级的阶段是级联的。 第一虚拟级包括第一充电单元，其接收来自多级的前一级的第一输入信号并由此充电;以及第一上拉晶体管，其在第一充电单元达到第一充电时输出时钟信号 水平。 第二虚拟级包括第二充电单元，其从第一虚拟级接收第二输入信号并由此被充电;以及第二上拉晶体管，当第二充电单元达到比第二充电电平高的第二充电电平时，输出时钟信号 第一充电水平。

公开(公告)号：US20100039575A1

公开(公告)日：2010-02-18

申请号：US12603529

申请日：2009-10-21

Applicant: Min-cheol LEE

Inventor： Min-cheol LEE

IPC: G02F1/1368

CPC classification number: G02F1/1393 ,  G02F1/136213 ,  G09G3/3648 ,  G09G2320/0219 ,  G09G2320/0223

Abstract: A liquid crystal display device includes a first substrate which comprises a plurality of pixels where a thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed, the first substrate including a gate line and a data line which insulatingly intersect each other; and a gate driver which applies a gate driving signal to the gate line, the thin film transistor including a gate electrode which is connected to the gate line; a source electrode which is connected to the data line; and a drain electrode which is connected to the pixel electrode, and the pixels being decreased in a value of Cp/(Cp+Clc+Cst) as going toward the gate driver (where, Cp: a sum of parasitic capacity between the gate electrode and the source electrode and parasitic capacity between the gate electrode and the drain electrode, Clc: liquid crystal capacity, and Cst: storage capacity).

Abstract translation: 液晶显示装置包括：第一基板，其包括形成薄膜晶体管和与薄膜晶体管电连接的像素电极的多个像素，第一基板包括栅极线和彼此绝缘地相交的数据线 ; 以及栅极驱动器，其对栅极线施加栅极驱动信号，所述薄膜晶体管包括连接到所述栅极线的栅电极; 连接到数据线的源电极; 以及连接到像素电极的漏电极，并且像素朝向栅极驱动器的Cp /（Cp + Clc + Cst）值减小（其中，Cp：栅电极之间的寄生电容之和 源电极和栅电极与漏电极之间的寄生电容，Clc：液晶容量，Cst：存储容量）。

公开(公告)号：US20080129717A1

公开(公告)日：2008-06-05

申请号：US11999329

申请日：2007-12-04

Applicant: Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-jin Jeon

Inventor： Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-jin Jeon

IPC: G06F3/038

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2320/0223

Abstract: In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Abstract translation: 在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

公开(公告)号：US20070296662A1

公开(公告)日：2007-12-27

申请号：US11763144

申请日：2007-06-14

Applicant: Min-Cheol Lee ,  Seung-Hwan Moon

Inventor： Min-Cheol Lee ,  Seung-Hwan Moon

IPC: G09G3/36

CPC classification number: G11C19/184 ,  G09G3/3677 ,  G09G2310/0286

Abstract: In a gate driving circuit and a display apparatus, the gate driving circuit comprises a plurality of stages. At least one of the stages comprises a pull-up section responsive to a first node signal; a pull-down section responsive to a second input signal; a discharging section discharging the first node signal in response to the second input signal; a first holding section responsive to the first clock signal, maintaining the first node signal at the off-voltage; and a second holding section responsive to the second clock signal, maintaining the first node signal at the off-voltage. The second holding section has a greater transistor width-to-length ratio than the first holding section. Therefore, an abnormal gate-on signal is less likely to occur, reducing driving defects of the display apparatus.

Abstract translation: 在栅极驱动电路和显示装置中，栅极驱动电路包括多个级。 至少一个级包括响应于第一节点信号的上拉部分; 响应于第二输入信号的下拉部分; 放电部分，响应于所述第二输入信号而放电所述第一节点信号; 响应于所述第一时钟信号的第一保持部分，将所述第一节点信号保持在所述截止电压; 以及响应于第二时钟信号的第二保持部分，将第一节点信号保持在截止电压。 第二保持部具有比第一保持部更大的晶体管宽度比。 因此，不太可能发生异常的接通信号，减少了显示装置的驱动缺陷。