公开(公告)号：US08448019B2

公开(公告)日：2013-05-21

申请号：US12971949

申请日：2010-12-17

申请人： Yoshiteru Ohnuki ,  Norihito Gomyo

发明人： Yoshiteru Ohnuki ,  Norihito Gomyo

IPC分类号： G06F11/00

CPC分类号： G06F11/1048

摘要： A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.

摘要翻译： 处理器包括累加器，向累加器输出数据的存储器，检测到数据中的错误时输出第一错误检测信号的错误检测器，输出指示存储器中发生错误的错误识别信号的错误标识符 输出作为第二误差检测信号的误差识别信号的误差识别信号保持器，保持第一误差检测信号并输出​​消除信号以停止累加器的累积处理的误差检测信号保持器，启动的第一计算器 基于第二错误检测信号和消除信号进行第一次计算，并且在经过计算周期之后输出校正开始信号;以及纠错器，其在接收到校正开始信号时校正数据的误差。

公开(公告)号：US20100095306A1

公开(公告)日：2010-04-15

申请号：US12638760

申请日：2009-12-15

申请人： Norihito GOMYO ,  Toshio Yoshida ,  Ryuichi Sunayama

发明人： Norihito GOMYO ,  Toshio Yoshida ,  Ryuichi Sunayama

IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F11/00 ,  G06F9/302

CPC分类号： G06F9/3851 ,  G06F9/30083 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3885

摘要： An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

摘要翻译： 算术装置同时处理多个线程，并且可以通过尽可能降低整个性能的劣化来继续该过程，尽管发生硬件错误。 算术装置100包括：指令执行电路101，其能够选择性地执行执行多个线程的指令序列的模式以及执行单线程的指令序列的模式; 和指示执行电路101切换线程模式的开关指示电路102。

公开(公告)号：US07383467B2

公开(公告)日：2008-06-03

申请号：US10986152

申请日：2004-11-12

申请人： Yasunobu Akizuki ,  Norihito Gomyo

发明人： Yasunobu Akizuki ,  Norihito Gomyo

IPC分类号： G06F11/00

CPC分类号： G06F11/1008 ,  G06F11/2236

摘要： A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops a program and interrupts a verification, the execution of the command retry is suppressed by assuming that no parity error is detected.

摘要翻译： 奇偶生成电路在确定完成期间反转所生成的奇偶校验数据以检测CSE条目的奇偶校验错误，以执行命令重试。 奇偶校验电路检测奇偶校验错误请求执行命令重试。 当命令重试机制停止程序并中断验证时，通过假设没有检测到奇偶校验错误来抑制命令重试的执行。

公开(公告)号：US08516303B2

公开(公告)日：2013-08-20

申请号：US12633840

申请日：2009-12-09

申请人： Norihito Gomyo ,  Ryuichi Sunayama

发明人： Norihito Gomyo ,  Ryuichi Sunayama

IPC分类号： G06F11/00

CPC分类号： G06F11/1405

摘要： A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

摘要翻译： 提供了一种处理器，其能够同时处理多个线程的指令序列，其实现与处理单个线程的指令序列的处理器中的成功率相当的重试成功率。 算术装置200具有用于执行多个线程的指令执行电路201，或者用于控制线程的执行状态或重新运行的执行控制电路202。

公开(公告)号：US08407714B2

公开(公告)日：2013-03-26

申请号：US12638760

申请日：2009-12-15

申请人： Norihito Gomyo ,  Toshio Yoshida ,  Ryuichi Sunayama

发明人： Norihito Gomyo ,  Toshio Yoshida ,  Ryuichi Sunayama

IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F15/76 ,  G06F11/00

CPC分类号： G06F9/3851 ,  G06F9/30083 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3885

摘要： An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

摘要翻译： 算术装置同时处理多个线程，并且可以通过尽可能降低整个性能的劣化来继续该过程，尽管发生硬件错误。 算术装置100包括：指令执行电路101，其能够选择性地执行执行多个线程的指令序列的模式以及执行单线程的指令序列的模式; 和指示执行电路101切换线程模式的开关指示电路102。

公开(公告)号：US20100088544A1

公开(公告)日：2010-04-08

申请号：US12633840

申请日：2009-12-09

申请人： Norihito GOMYO ,  Ryuichi SUNAYAMA

发明人： Norihito GOMYO ,  Ryuichi SUNAYAMA

IPC分类号： G06F11/14

CPC分类号： G06F11/1405

摘要： A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

摘要翻译： 提供了一种处理器，其能够同时处理多个线程的指令序列，其实现与处理单个线程的指令序列的处理器中的成功率相当的重试成功率。 算术装置200具有用于执行多个线程的指令执行电路201，或者用于控制线程的执行状态或重新运行的执行控制电路202。

公开(公告)号：US20060129897A1

公开(公告)日：2006-06-15

申请号：US11153427

申请日：2005-06-16

申请人： Norihito Gomyo

发明人： Norihito Gomyo

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/0721 ,  G06F11/0772 ,  G06F11/0781

摘要： In the instruction control apparatus having an instruction processing suspension unit and an error detection unit, in order to improve the reliability of the apparatus, the apparatus is configured in such a way that when an error occurs to certain hardware resources in the instruction processing apparatus, error detection is conducted if instruction processing is under way, but error detection is deterred if instruction processing is in suspension, and the scope of the error which cannot be deterred during the suspension of instruction processing is made narrower than the scope of the error which cannot be deterred during instruction processing.

公开(公告)号：US20060026461A1

公开(公告)日：2006-02-02

申请号：US10986152

申请日：2004-11-12

申请人： Yasunobu Akizuki ,  Norihito Gomyo

发明人： Yasunobu Akizuki ,  Norihito Gomyo

IPC分类号： G06F11/00

CPC分类号： G06F11/1008 ,  G06F11/2236

摘要： A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops a program and interrupts a verification, the execution of the command retry is suppressed by assuming that no parity error is detected.

摘要翻译： 奇偶生成电路在确定完成期间反转所生成的奇偶校验数据以检测CSE条目的奇偶校验错误，以执行命令重试。 奇偶校验电路检测奇偶校验错误请求执行命令重试。 当命令重试机制停止程序并中断验证时，通过假设没有检测到奇偶校验错误来抑制命令重试的执行。

公开(公告)号：US20110314262A1

公开(公告)日：2011-12-22

申请号：US13220006

申请日：2011-08-29

申请人： Atsushi FUSEJIMA ,  Norihito Gomyo

发明人： Atsushi FUSEJIMA ,  Norihito Gomyo

IPC分类号： G06F9/30

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/34 ,  G06F9/383

摘要： A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among the storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of decoding of the instruction. The prefetch request circuit includes a latch unit to hold, when a state in which the respective instruction flows to access the storage area are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and a prefetch request signal output unit to output a prefetch request signal to request the prefetch every time when the instruction flow is executed, based on an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows.

摘要翻译： 在处理器设备中提供预取请求电路。 处理器装置具有层次化的存储区域，并且当在指令解码时执行通过多流程扩展获得的用于一个指令的各个指令流时，可以预取在存储区域中的适当存储区域之间使用的地址数据。 预取请求电路包括：锁存单元，当指定以最大可指定数据传送量执行相应指令访问存储区域的状态时，保持多流程扩展期间的状态; 以及预取请求信号输出单元，用于基于所述锁存单元的输出信号和指示各个指令流的执行定时的信号，输出预取请求信号，以在每次执行指令流时请求预取。

公开(公告)号：US20110161764A1

公开(公告)日：2011-06-30

申请号：US12971949

申请日：2010-12-17

申请人： Yoshiteru OHNUKI ,  Norihito Gomyo

发明人： Yoshiteru OHNUKI ,  Norihito Gomyo

IPC分类号： G06F11/273

CPC分类号： G06F11/1048

摘要： A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.

摘要翻译： 处理器包括累加器，向累加器输出数据的存储器，检测到数据中的错误时输出第一错误检测信号的错误检测器，输出指示存储器中发生错误的错误识别信号的错误标识符 输出作为第二误差检测信号的误差识别信号的误差识别信号保持器，保持第一误差检测信号并输出​​消除信号以停止累加器的累积处理的误差检测信号保持器，启动的第一计算器 基于第二错误检测信号和消除信号进行第一次计算，并且在经过计算周期之后输出校正开始信号;以及纠错器，其在接收到校正开始信号时校正数据的误差。