公开(公告)号：US08130298B2

公开(公告)日：2012-03-06

申请号：US12027283

申请日：2008-02-07

申请人： Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Paul A. Niekrewicz

发明人： Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Paul A. Niekrewicz

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H04N5/235 ,  H04N5/35527 ,  H04N5/3745

摘要： Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

摘要翻译： 公开了包含标准光电二极管的像素成像电路的实施例。 然而，成像电路用反馈回路修改以在光感测范围的第一部分（例如，在较高的光强度范围）提供第一光响应，并且在光的第二部分上提供第二灵敏度敏感的光响应 感测范围（即，在较低的光强度范围），从而延长电路的动态覆盖范围。 还公开了相关的成像方法和体现在机器可读介质中并用于成像电路设计过程中的设计结构的实施例。

公开(公告)号：US20090201394A1

公开(公告)日：2009-08-13

申请号：US12027283

申请日：2008-02-07

申请人： Phillip L. Corson ,  Mete Erturk ,  Ezra D.B. Hall ,  Paul A. Niekrewicz

发明人： Phillip L. Corson ,  Mete Erturk ,  Ezra D.B. Hall ,  Paul A. Niekrewicz

IPC分类号： H04N5/335

CPC分类号： H04N5/235 ,  H04N5/35527 ,  H04N5/3745

摘要： Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

摘要翻译： 公开了包含标准光电二极管的像素成像电路的实施例。 然而，成像电路用反馈回路修改以在光感测范围的第一部分（例如，在较高的光强度范围）提供第一光响应，并且在光的第二部分上提供第二灵敏度敏感的光响应 感测范围（即，在较低的光强度范围），从而延长电路的动态覆盖范围。 还公开了相关的成像方法和体现在机器可读介质中并用于成像电路设计过程中的设计结构的实施例。

公开(公告)号：US08239811B2

公开(公告)日：2012-08-07

申请号：US12053705

申请日：2008-03-24

申请人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

发明人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： H04Q9/00 ,  H01L22/12 ,  H01L22/14 ,  H01L22/26 ,  H01L23/64 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.

摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。

公开(公告)号：US06629292B1

公开(公告)日：2003-09-30

申请号：US09680879

申请日：2000-10-06

申请人： Phillip L. Corson ,  Gary R. Holsopple ,  Jason M. Parry ,  William F. Pokorny

发明人： Phillip L. Corson ,  Gary R. Holsopple ,  Jason M. Parry ,  William F. Pokorny

IPC分类号： G06F1750

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2924/0002 ,  H01L2924/00

摘要： High resolution gray scale graphical images are formed in a semiconductor substrate by the use of two or more levels of indicia having a plurality of image segments and having a continuous conductive line formed in the surface of the substrate, each image segment includes a portion of said continuous conductive line and a contrasting material providing pixels in which the width of the line within a segment varies in relationship to gray scale levels in the graphic image to be formed. Providing a graphic image to be converted; converting the graphic image to a gray level, two dimensional bit mapped converting the bit mapped image into a set of parallel lines of varying width; each line comprising a single continuous segment in which the width varies based on the density of the gray level required to form the gray level image; and transferring the set of lines to a pattern of conductor/insulator lines on a substrate.

摘要翻译： 通过使用具有多个图像段的两个或更多个级别的标记并且在衬底的表面中形成有连续导电线，在半导体衬底中形成高分辨率灰度图形图像，每个图像段包括所述 连续导电线和提供像素的对比材料，其中片段内的线的宽度与要形成的图形图像中的灰度级别相关。 提供要转换的图形图像; 将图形图像转换为灰度级，二维比特映射将位映射图像转换成一组不同宽度的平行线; 每条线包括单个连续段，其中宽度基于形成灰度级图像所需的灰度级的密度而变化; 以及将所述一组线转移到衬底上的导体/绝缘体线的图案。

公开(公告)号：US20090240452A1

公开(公告)日：2009-09-24

申请号：US12053705

申请日：2008-03-24

申请人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D.B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

发明人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D.B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

IPC分类号： G01R23/16

CPC分类号： H04Q9/00 ,  H01L22/12 ,  H01L22/14 ,  H01L22/26 ,  H01L23/64 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.

摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 这些实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。

公开(公告)号：US06912165B2

公开(公告)日：2005-06-28

申请号：US10604867

申请日：2003-08-22

申请人： Phillip L. Corson ,  Harold Pilo

发明人： Phillip L. Corson ,  Harold Pilo

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/419

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/419 ,  G11C2207/2254

摘要： Disclosed is a method and structure that controls an output driver by generating an output data path clock signal from a system clock signal and timing the programmable impedance of the output driver according to the output data path clock signal. The method/structure controls the timing of the line driver circuits according to the output data path clock signal. By timing the programmable impedance according to the output data path clock signal, the timing of delivery of an impedance control signal is coordinated with the timing of delivery of data. The method/structure also performs impedance updates on the output driver more frequently during initialization cycles than in cycles that occur after the initialization cycles expire using at least two differently timed clock dividers and a counter.

摘要翻译： 公开了一种通过从系统时钟信号产生输出数据路径时钟信号并根据输出数据路径时钟信号对输出驱动器的可编程阻抗进行定时来控制输出驱动器的方法和结构。 该方法/结构根据输出数据路径时钟信号来控制线路驱动电路的定时。 通过根据输出数据路径时钟信号对可编程阻抗进行定时，将阻抗控制信号的传递时序与数据传送的时序协调。 该方法/结构还在初始化周期期间更频繁地对输出驱动器进行阻抗更新，而不是在使用至少两个不同时间的时钟分频器和计数器的初始化周期到期后发生的周期。