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1.发明申请SYSTEM AND METHOD FOR WIRELESS AND DYNAMIC INTRA-PROCESS MEASUREMENT OF INTEGRATED CIRCUIT PARAMETERS 有权集成电路参数的无线和动态内部过程测量系统与方法公开(公告)号：US20090240452A1
公开(公告)日：2009-09-24
申请号：US12053705
申请日：2008-03-24
申请人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D.B. Hall , Anthony J. Perri , Sebastian T. Ventrone
发明人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D.B. Hall , Anthony J. Perri , Sebastian T. Ventrone
IPC分类号： G01R23/16
CPC分类号： H04Q9/00 , H01L22/12 , H01L22/14 , H01L22/26 , H01L23/64 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.
摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 这些实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。
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2.发明授权System and method for wireless and dynamic intra-process measurement of integrated circuit parameters 有权集成电路参数的无线和动态过程内测量的系统和方法公开(公告)号：US08239811B2
公开(公告)日：2012-08-07
申请号：US12053705
申请日：2008-03-24
申请人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D. B. Hall , Anthony J. Perri , Sebastian T. Ventrone
发明人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D. B. Hall , Anthony J. Perri , Sebastian T. Ventrone
CPC分类号： H04Q9/00 , H01L22/12 , H01L22/14 , H01L22/26 , H01L23/64 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.
摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。
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3.发明申请Integrated Circuit Chip Design Flow Methodology Including Insertion of On-Chip or Scribe Line Wireless Process Monitoring and Feedback Circuitry 有权集成电路芯片设计流程方法包括插入片上或划线无线过程监控和反馈电路公开(公告)号：US20090239313A1
公开(公告)日：2009-09-24
申请号：US12343686
申请日：2008-12-24
CPC分类号： G06F17/5045 , G01R31/2884 , G01R31/3025 , G06F2217/12 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).
摘要翻译： 公开了设计和制造系统以及相关方法的实施例，其允许在晶片制造期间进行设计分析和插入过程内监控电路。 这些实施例使用预定义的内部过程监视电路库和将不同监控电路与不同IC芯片组件链接的互相关表。 具体地，这些实施例分析集成电路芯片设计数据以识别设计到芯片中的部件。 然后，从库中选择一个或多个进程内监控电路，并且修改设计数据以包括所选择的监视电路。
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公开(公告)号：US20080186069A1
公开(公告)日：2008-08-07
申请号：US12099423
申请日：2008-04-08
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
IPC分类号： H03K3/00
CPC分类号： G11C5/145 , H03K3/356008
摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译： 本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号 ，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。
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公开(公告)号：US20080062748A1
公开(公告)日：2008-03-13
申请号：US11530981
申请日：2006-09-12
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
IPC分类号： G11C11/00
摘要： The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译： 本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号 分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。
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6.发明授权Asynchronous packet based dual port link list header and data credit management structure 有权基于异步数据包的双端口链路列表头和数据信用管理结构公开(公告)号：US07752355B2
公开(公告)日：2010-07-06
申请号：US10832658
申请日：2004-04-27
IPC分类号： G06F5/00
CPC分类号： G06F13/4059
摘要： An asynchronous data transfer interface is provided across a boundary that allows high bandwidth data transfers which are packet based as defined by PCI_Express architecture, and has general utility in processor-based applications like servers, desktop applications, and mobile applications. A shared set of multi-port RAM buffers allow both an application layer AL and a transaction layer TL access to a communication protocol layer in a defined process that allows both the application layer AL and the transaction layer TL to read and manage the buffers in a 16 byte boundary in a manner that allows a data credit to be decoupled from a header credit.
摘要翻译： 跨越边界提供异步数据传输接口，允许高速带宽数据传输，这些数据传输是由PCI_Express架构定义的基于分组的，并且在基于处理器的应用程序（如服务器，桌面应用程序和移动应用程序）中具有通用功能。 共享的一组多端口RAM缓冲器允许应用层AL和事务层TL在定义的过程中访问通信协议层，允许应用层AL和事务层TL两者读取和管理缓冲区中的缓冲区 16字节边界以允许从标题信用中分离数据信用的方式。
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公开(公告)号：US07495492B2
公开(公告)日：2009-02-24
申请号：US11530981
申请日：2006-09-12
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
IPC分类号： H03K3/289
摘要： The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译： 本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号 分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。
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公开(公告)号：US07966589B2
公开(公告)日：2011-06-21
申请号：US12099423
申请日：2008-04-08
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
IPC分类号： G06F17/50
CPC分类号： G11C5/145 , H03K3/356008
摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译： 本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号 ，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。
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9.发明申请INTEGRATED CIRCUIT CHIP INCORPORATING EMBEDDED THERMAL RADIATORS FOR LOCALIZED, ON-DEMAND, HEATING AND A SYSTEM AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT CHIP 失效集成电路芯片，用于本地化，点燃，加热和系统的嵌入式热分解器以及用于设计这种集成电路芯片的方法公开(公告)号：US20120168416A1
公开(公告)日：2012-07-05
申请号：US12984638
申请日：2011-01-05
CPC分类号： H05B1/0227 , G05D23/1934
摘要： Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.
摘要翻译： 公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。 芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。 温度传感器可以位于与TSZ相邻的半导体衬底中。 热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。 温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。 此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。 还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。
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10.发明授权公开(公告)号：US07937560B2
公开(公告)日：2011-05-03
申请号：US12121292
申请日：2008-05-15
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
CPC分类号： G06F9/3867 , G06F1/32 , G06F1/3287 , G06F11/1407 , G06F11/1441 , Y02D10/171
摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译： 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。
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