公开(公告)号：US20060150063A1

公开(公告)日：2006-07-06

申请号：US10861667

申请日：2004-06-04

申请人： Robert Allen Hillman

发明人： Robert Allen Hillman

IPC分类号： G11C29/00

CPC分类号： G06F11/1012

摘要： A method and a system for the detection and correction of errors in memory systems is disclosed. In one embodiment, a method of error detection in a memory system having a plurality (m>1) of memory devices includes generating check bits for each of a plurality of data sets, dividing each memory device into a plurality (n>1) of segments. The plurality of data sets are interleaved to form a plurality (p>1) of words. Each word includes at least one segment from two or more of the memory devices. Detection and correction may utilize one or more parallel Reed-Solomon decoder and encoder. The system and method allow for the efficient detection and/or correction of memory device errors and bit errors in one or more memory devices.

摘要翻译： 公开了一种用于检测和校正存储器系统中的错误的方法和系统。 在一个实施例中，一种具有多个（m> 1）存储器件的存储器系统中的错误检测方法包括：产生用于多个数据组中的每一个的校验位，将每个存储器件分成多个（n≥1）个 细分。 多个数据集被交织以形成多个（p> 1）个字。 每个单词包括来自两个或更多个存储器件的至少一个段。 检测和校正可以利用一个或多个并行Reed-Solomon解码器和编码器。 该系统和方法允许对一个或多个存储器件中的存储器件错误和位错误的有效检测和/或校正。

公开(公告)号：US20090158088A1

公开(公告)日：2009-06-18

申请号：US12336026

申请日：2008-12-16

申请人： Robert Allen Hillman ,  Mark Steven Conrad

发明人： Robert Allen Hillman ,  Mark Steven Conrad

IPC分类号： G06F11/16

CPC分类号： G06F11/184 ,  G06F11/00 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/181 ,  G06F11/187 ,  G06F11/20 ,  G06F2201/81 ,  G06F2201/88

摘要： The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached. The milestone may be a predetermined time interval or any other event that may be defined by a user.

摘要翻译： 公开了容错或自校正计算机系统。 例如，提供有可能由空间辐射引起的故障的各种保护措施的计算机系统。 系统的可靠性得到提高，可以通过定期清洗组件而不是等待检测到错误来实现。 因此，长时间未检测到的错误不允许传播并进一步损坏系统。 提供三个或更多个处理器以并行操作，并且提供控制器以从处理器接收信号，并且使用投票逻辑来确定多数信号值。 以这种方式，当来自一个处理器的信号与多数信号不同时，控制器可以检测到错误。 该系统还设置有用于在达到预定里程碑之后重新同步处理器的擦洗模块。 里程碑可以是预定的时间间隔或可由用户定义的任何其他事件。

公开(公告)号：US07673186B2

公开(公告)日：2010-03-02

申请号：US11449510

申请日：2006-06-07

申请人： Robert Allen Hillman

发明人： Robert Allen Hillman

IPC分类号： G06F11/00

CPC分类号： G06F13/409 ,  H05K1/0262 ,  H05K2201/044 ,  H05K2201/10174 ,  Y02D10/14 ,  Y02D10/151

摘要： Power supply voltage of a PCI or a similar communication bus interface is separated from one or more other power supply voltages on a backplane, on boards insertable into the backplane, and on the bus interface components of the boards. The power supply of the bus interface (VIO) is provided to cold spare boards inserted into the backplane, while the other voltages are not provided to the cold spare boards. Availability of the VIO on the cold spare boards prevents the VIO clamping diodes on the PCI I/O lines from grounding the PCI bus. Cold spare capability is thus provided to systems with PCI and similar communication buses.

摘要翻译： PCI或类似通信总线接口的电源电压与背板上的一个或多个其他电源电压，可插入背板的板上以及板上总线接口组件分离。 总线接口（VIO）的电源提供给插入背板的冷备用板，而其他电压不提供给冷备用板。 在冷备用板上提供VIO可以防止PCI I / O线上的VIO钳位二极管接地PCI总线。 因此，将冷备用能力提供给具有PCI和类似通信总线的系统。

公开(公告)号：US07467326B2

公开(公告)日：2008-12-16

申请号：US10418713

申请日：2003-04-17

申请人： Robert Allen Hillman ,  Mark Steven Conrad

发明人： Robert Allen Hillman ,  Mark Steven Conrad

IPC分类号： G06F11/00

CPC分类号： G06F11/184 ,  G06F11/00 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/181 ,  G06F11/187 ,  G06F11/20 ,  G06F2201/81 ,  G06F2201/88

摘要： The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached. The milestone may be a predetermined time interval or any other event that may be defined by a user.

摘要翻译： 公开了容错或自校正计算机系统。 例如，提供有可能由空间辐射引起的故障的各种保护措施的计算机系统。 系统的可靠性得到提高，可以通过定期清洗组件而不是等待检测到错误来实现。 因此，长时间未检测到的错误不允许传播并进一步损坏系统。 提供三个或更多个处理器以并行操作，并且提供控制器以从处理器接收信号，并且使用投票逻辑来确定多数信号值。 以这种方式，当来自一个处理器的信号与多数信号不同时，控制器可以检测到错误。 该系统还设置有用于在达到预定里程碑之后重新同步处理器的擦洗模块。 里程碑可以是预定的时间间隔或可由用户定义的任何其他事件。

公开(公告)号：US20070285851A1

公开(公告)日：2007-12-13

申请号：US11449510

申请日：2006-06-07

申请人： Robert Allen Hillman

发明人： Robert Allen Hillman

IPC分类号： H02H7/00

CPC分类号： G06F13/409 ,  H05K1/0262 ,  H05K2201/044 ,  H05K2201/10174 ,  Y02D10/14 ,  Y02D10/151

摘要： Power supply voltage of a PCI or a similar communication bus interface is separated from one or more other power supply voltages on a backplane, on boards insertable into the backplane, and on the bus interface components of the boards. The power supply of the bus interface (VIO) is provided to cold spare boards inserted into the backplane, while the other voltages are not provided to the cold spare boards. Availability of the VIO on the cold spare boards prevents the VIO clamping diodes on the PCI I/O lines from grounding the PCI bus. Cold spare capability is thus provided to systems with PCI and similar communication buses.

摘要翻译： PCI或类似通信总线接口的电源电压与背板上的一个或多个其他电源电压，可插入背板的板上以及板上总线接口组件分离。 总线接口（VIO）的电源提供给插入背板的冷备用板，而其他电压不提供给冷备用板。 在冷备用板上提供VIO可以防止PCI I / O线上的VIO钳位二极管接地PCI总线。 因此，将冷备用能力提供给具有PCI和类似通信总线的系统。