公开(公告)号：US08188755B2

公开(公告)日：2012-05-29

申请号：US12685992

申请日：2010-01-12

Applicant: Roberto Alini ,  Roberto Casiraghi

Inventor： Roberto Alini ,  Roberto Casiraghi

IPC: G01R27/26

CPC classification number: G03B21/53 ,  G01R27/2605 ,  G02B7/08 ,  G03B3/10 ,  G03B13/34

Abstract: A driver and capacitance measuring circuit includes a voltage source that selectively generates an output voltage at a first node during a driver mode to alter a capacitance of a device that is connected to the first node and that has a variable capacitance. A current source selectively provides one of a charging and discharging current at the first node during a measurement mode. A capacitance calculating circuit samples a voltage at the first node during the measurement node, determines a voltage change rate of the first node during the measurement mode and calculates the capacitance of the device based on the voltage change rate and a value of the one of the charging and discharging current.

Abstract translation: 驱动器和电容测量电路包括电压源，其在驱动器模式期间选择性地在第一节点处产生输出电压，以改变连接到第一节点并具有可变电容的装置的电容。 在测量模式期间，电流源选择性地提供第一节点处的充电和放电电流之一。 电容计算电路在测量节点期间对第一节点处的电压进行采样，在测量模式期间确定第一节点的电压变化率，并基于电压变化率和电压变化率的一个值计算器件的电容 充放电电流。

公开(公告)号：US06512645B1

公开(公告)日：2003-01-28

申请号：US09393231

申请日：1999-09-09

Applicant: Giuseppe Patti ,  Roberto Alini ,  Elango Pakriswamy

Inventor： Giuseppe Patti ,  Roberto Alini ,  Elango Pakriswamy

IPC: G11B509

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09

Abstract: A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, a current sink circuit which is coupled to the write head terminal and a bootstrap circuit coupled to the current sink circuit. When reversing the direction of current flow through the write head so that current is drawn from the write head from the write head terminal, the bootstrap circuit and the current sink circuit are activated. When the current in the write head nears and/or slightly surpasses the desired destination current level, the bootstrap circuit is deactivated and the pull-up device is thereafter immediately activated for a predetermined period of time.

Abstract translation: 公开了一种用于控制磁盘存储装置的写入头的方法和电路。 电路包括耦合到写头的端子的上拉装置，耦合到写入头端子的电流吸收电路和耦合到电流吸收电路的自举电路。 当逆向通过写入头的电流的方向使得电流从写入头从写入头抽出时，自举电路和电流吸收电路被激活。 当写头中的电流接近和/或稍微超过期望的目的地电流电平时，自举电路被去激活，然后上拉装置立即激活预定时间段。

公开(公告)号：US5644267A

公开(公告)日：1997-07-01

申请号：US455850

申请日：1995-05-31

Applicant: Francesco Brianti ,  Roberto Alini ,  Valerio Pisati ,  Paolo Gadducci

Inventor： Francesco Brianti ,  Roberto Alini ,  Valerio Pisati ,  Paolo Gadducci

IPC: H03H11/04 ,  H03F3/68

CPC classification number: H03H11/0433

Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i.sub.K1, i.sub.K2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

Abstract translation: 一种高通滤波器，特别适用于高频应用，并且包括至少一个输入端（IN）和至少一个输出端（OUT）的类型，其间被定义为传递函数（FdT），并被插入一个二次电池 包括一系列跨导级（2,3,4,5）的（18）包括连接在所述二次电池（18）的一对级（2,3）之间的可变电流（iK1，iK2）的发电机电路（29） ）和电压基准（GND）。 所述发生器允许在滤波器（20）的传递函数（FdT）中引入可编程零点。

公开(公告)号：US5495201A

公开(公告)日：1996-02-27

申请号：US145989

申请日：1993-10-29

Applicant: Roberto Alini ,  Maurizio Zuffada ,  David Moloney ,  Silvano Gornati

Inventor： Roberto Alini ,  Maurizio Zuffada ,  David Moloney ,  Silvano Gornati

IPC: H03F1/32 ,  H03F3/45 ,  H03H11/04 ,  G06G7/12

CPC classification number: H03F3/45071 ,  H03F1/3211 ,  H03H11/0422

Abstract: A transconductor stage for high-frequency filters operated on a low voltage supply, being of a type which comprises an input circuit portion having signal inputs, further comprises a pair of interconnected differential cells (2,3) being associated each with a corresponding signal input. Each cell incorporates at least one pair of bipolar transistors (Q1,Q2;Q3,Q4) having at least one corresponding terminal thereof (e.g. the emitter terminal) connected in common.

Abstract translation: 一种用于在低电压电源上工作的高频滤波器的跨导电压级，其包括具有信号输入的输入电路部分的类型，还包括一对互连的差分单元（2,3），其中每一个具有对应的信号输入 。 每个单元包含至少一对具有共同连接的至少一个对应端子（例如发射极端子）的双极晶体管（Q1，Q2; Q3，Q4）。

公开(公告)号：US20050254159A1

公开(公告)日：2005-11-17

申请号：US10843823

申请日：2004-05-12

Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC: G11B5/09 ,  G05F3/26 ,  G11B5/00 ,  G11B5/02 ,  H02M3/07

CPC classification number: G11B5/09 ,  G11B2005/0016 ,  H02M3/073

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

Abstract translation: 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间期间进入反向偏置。

公开(公告)号：US20050231843A1

公开(公告)日：2005-10-20

申请号：US10824096

申请日：2004-04-14

Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC: G11B5/09 ,  G05F3/26 ,  G11B5/02 ,  H04L25/02

CPC classification number: G11B5/02

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

Abstract translation: 用于通过互连或柔性传输线连接到写入头的写入头来驱动写入电流的写入驱动器。 写驱动器包括将写驱动器的输出阻抗与互连的奇特特性阻抗匹配的电路，并且包括产生到写头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，其操作以在互连的传输延迟的两倍的初始周期期间在输出电阻器上保持零电压降。

公开(公告)号：US06456148B2

公开(公告)日：2002-09-24

申请号：US09839511

申请日：2001-04-20

Applicant: Giuseppe Patti ,  Roberto Alini ,  Gilles P. DeNoyer

Inventor： Giuseppe Patti ,  Roberto Alini ,  Gilles P. DeNoyer

IPC: H03K1756

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09

Abstract: A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, for selectively providing a current to the write head though the write head terminal. The circuit further includes parallel-connected current sink circuits, each of which is coupled to the write head terminal and selectively activated to draw current from the write head via the write head terminal. A first transistor is connected in series between the pull-up device and the write head terminal and biased to provide a voltage differential between the write head terminal and the pull-up device. A second transistor is connected in series between the write head terminal and the current sink circuits and biased to provide a voltage differential between the write head terminal and the current sink circuits.

Abstract translation: 公开了一种用于控制磁盘存储装置的写入头的方法和电路。 该电路包括耦合到写入头的终端的上拉装置，用于通过写入头终端选择性地向写入头提供电流。 电路还包括并联连接的电流吸收电路，每个电路都耦合到写入头终端，并被选择性地激活以经由写头终端从写入头抽取电流。 第一晶体管串联连接在上拉器件和写入端子之间，并被偏置以在写入头端子和上拉器件之间提供电压差。 第二晶体管串联连接在写入头端子和电流吸收电路之间，并被偏置以在写入头端子和电流吸收电路之间提供电压差。

公开(公告)号：US06362681B1

公开(公告)日：2002-03-26

申请号：US09461782

申请日：1999-12-15

Applicant: Giacomino Bollati ,  Roberto Alini ,  Daniele Ottini ,  Melchiorre Bruccoleri

Inventor： Giacomino Bollati ,  Roberto Alini ,  Daniele Ottini ,  Melchiorre Bruccoleri

IPC: H03K500

CPC classification number: H03H11/0422

Abstract: A low pass filter with programmable equalization includes at least one biquadratic cell and a converter of the input voltage into a current, proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell to introduce two real and opposed zeros in the transfer function of the filter. The low pass filter includes two structurally similar circuits functionally connected in cascade. Each circuit includes a biquadratic cell and an input stage having two outputs injecting, through a first current output, the current to an input capacitor of the respective biquadratic cell, by a direct coupling in a first of the two circuits and in an inverted manner in the second of the two circuits. A second voltage output is coupled to an input of the respective biquadratic cell.

Abstract translation: 具有可编程均衡的低通滤波器包括至少一个二次电池和将输入电压转换为与输入电压的导数成比例的电流的转换器，其被注入到二次电池的节点上以引入两个实际和相对的零 在滤波器的传递函数中。 低通滤波器包括在功能上串联连接的两个结构相似的电路。 每个电路包括一个二次电池单元和一个具有两个输出端的输入级，输出端通过第一电流输出将电流通过两个电路中的第一个电路中的直接耦合并以相反的方式在相应的二次电池单元的输入电容器中注入 这两个电路中的第二个。 第二电压输出耦合到相应的双二次电池的输入端。

公开(公告)号：US06359743B1

公开(公告)日：2002-03-19

申请号：US09197122

申请日：1998-11-20

Applicant: Giuseppe Patti ,  Eugene C. Lee ,  Roberto Alini

Inventor： Giuseppe Patti ,  Eugene C. Lee ,  Roberto Alini

IPC: G11B502

CPC classification number: G11B5/012 ,  G11B2005/0016

Abstract: An apparatus (and method) is provided that reduces thermal interference in the read signal of a disk drive. A variable or programmable resistance is used to change the transfer function of a filter in the read channel of the disk drive to filter the read signal. The filter has a first transfer function (first cut-off frequency) related to the programmed resistance during normal operation of the disk drive (i.e. when thermal interference is not detected). When thermal interference is detected in the read signal, the resistance is programmed to another value resulting in the filter having a second transfer function (second cut-off frequency). The resistance element is variable or programmable to different values resulting in different programmable transfer functions (or one of a multitude of cut-off frequencies) for the filter. In the preferred embodiment, detection of thermal interference increases the cut-off frequency of the filter thereby filtering, or reducing the effects of, the thermal interference in the read signal.

Abstract translation: 提供了减少磁盘驱动器的读取信号中的热干扰的装置（和方法）。 使用可变或可编​​程电阻来改变磁盘驱动器的读通道中的滤波器的传递函数，以过滤读取信号。 滤波器在磁盘驱动器的正常操作期间（即，当未检测到热干扰时）具有与编程电阻相关的第一传递函数（第一截止频率）。 当在读取信号中检测到热干扰时，电阻被编程为另一个值，导致滤波器具有第二传递函数（第二截止频率）。 电阻元件可变或可编​​程为不同的值，导致滤波器的不同可编程传输功能（或多个截止频率之一）。 在优选实施例中，热干扰的检测增加了滤波器的截止频率，从而过滤或减少了读取信号中的热干扰的影响。

公开(公告)号：US5963065A

公开(公告)日：1999-10-05

申请号：US787301

申请日：1997-01-24

Applicant: Roberto Alini ,  Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Valerio Pisati

Inventor： Roberto Alini ,  Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Valerio Pisati

IPC: H03F3/30 ,  H03F3/34 ,  H03F3/26

CPC classification number: H03F3/3077

Abstract: A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).

Abstract translation: 低失调放大器具有由推挽装置中的npn晶体管和pnp晶体管构成的输出级和驱动级。 后者包括电流镜电路，其在其输入支路中具有与第一恒定电流发生器串联的pnp晶体管，并且在其输出支路中具有npn晶体管，以及两个互补双极晶体管，其中集电极连接到输出端 端子和基极连接到放大器的输入端子。 驱动器级的pnp晶体管的发射极通过第二恒流发生器连接到电源的正极端子，并连接到输出级的npn晶体管的基极，驱动器级的npn晶体管的发射极 通过电流镜电路的输出支路的npn晶体管和输出级的pnp晶体管的基极连接到电源的负极。 放大器具有非常低或零偏移（Vos = Vout-Vin）。