公开(公告)号：US5471152A

公开(公告)日：1995-11-28

申请号：US133588

申请日：1993-10-08

Applicant: Tushar Gheewala ,  Rustam Mehta ,  Prab Varma

Inventor： Tushar Gheewala ,  Rustam Mehta ,  Prab Varma

IPC: G01R31/30 ,  G01R31/3185 ,  G01R31/00 ,  G01R31/02

CPC classification number: G01R31/3016 ,  G01R31/3185

Abstract: A storage element for testing delay paths in integrated circuits is described. The storage element may be used in integrated circuits having matrices of probe and sense lines. The storage element generates a logic transition on an input to a delay path, the logic transition being closely synchronized with a clock signal. The storage element comprises a data input and a data output coupled to the input to the delay path. A master latch receives data from the data input through a first switch, the first switch being controlled by the complement of the clock signal. A slave latch receives data from the master latch through a second switch, the second switch being controlled by the true of the clock signal. A first sense input loads a first logic state into the master latch through a third switch, the first sense input being coupled to one of the IC's sense lines. The third switch is controlled by one of the IC's probe lines. A second sense input loads a second logic state into the slave latch through a fourth switch, the second sense input being coupled to another one of the IC's sense lines. The fourth switch is controlled by a second control signal. The second logic state replaces the first logic state in the slave latch upon application of the clock signal. The desired signal transition is generated where the first logic state is different from the second logic state.

Abstract translation: 描述用于测试集成电路中的延迟路径的存储元件。 存储元件可以用于具有探针和感测线的矩阵的集成电路中。 存储元件在延迟路径的输入上产生逻辑转换，逻辑转换与时钟信号紧密同步。 存储元件包括数据输入和耦合到延迟路径的输入的数据输出。 主锁存器通过第一开关从数据输入端接收数据，第一开关由时钟信号的补码控制。 从锁存器通过第二开关从主锁存器接收数据，第二开关由时钟信号的真实来控制。 第一感测输入通过第三开关将第一逻辑状态加载到主锁存器中，第一感测输入耦合到IC的感测线之一。 第三个开关由IC的探针线之一控制。 第二感测输入通过第四开关将第二逻辑状态加载到从锁存器中，第二感测输入耦合到IC的感测线中的另一个。 第四开关由第二控制信号控制。 第二逻辑状态在施加时钟信号时替代从锁存器中的第一逻辑状态。 产生期望的信号转换，其中第一逻辑状态不同于第二逻辑状态。

公开(公告)号：US4460982A

公开(公告)日：1984-07-17

申请号：US380149

申请日：1982-05-20

Applicant: Lubin Gee ,  Pearl Cheng ,  Yogendra Bobra ,  Rustam Mehta

Inventor： Lubin Gee ,  Pearl Cheng ,  Yogendra Bobra ,  Rustam Mehta

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/32 ,  G11C11/40

CPC classification number: G11C16/32 ,  G11C16/10 ,  G11C16/14

Abstract: An E.sup.2 PROM is disclosed which provides automatic programming verification. Before data is written into the cells, the cells are automatically erased. The contents of the cells are checked to verify that erasing has been completed. If it has not, erasing is continued until the cells are erased. When data is written into the cells, the writing of the data into the cells continues until programming is verified. The verification is conducted at potentials other than the normal reference potential to assure that the cells are well programmed with either binary zeroes or binary ones.

Abstract translation: 公开了一种提供自动编程验证的E2PROM。 在将数据写入单元格之前，单元将被自动擦除。 检查单元的内容以验证擦除是否已完成。 如果没有，则继续擦除直到单元被擦除。 当数据写入单元格时，将数据写入单元继续，直到编程被验证。 验证在除了正常参考电位之外的电位下进行，以确保电池具有二进制零或二进制零编程。

公开(公告)号：US5436801A

公开(公告)日：1995-07-25

申请号：US120148

申请日：1993-09-09

Applicant: Tushar Gheewala ,  Rustam Mehta ,  Timothy Saxe

Inventor： Tushar Gheewala ,  Rustam Mehta ,  Timothy Saxe

IPC: H01L23/528 ,  H01R9/00

CPC classification number: H01L23/5286 ,  H01L2924/0002

Abstract: An integrated circuit structure which employs at least two metal levels overlying an array of circuit elements. Each metal level contains signal routing resources which can be used for supplying power and interconnecting circuit elements. The metal levels include a first metal level directly overlying the array of circuit elements, intermediate metal levels (if there are more than two metal levels), and a top metal level overlying all other metal levels. Power carrying tracks are disposed in the top metal level. Power antennae are disposed in the first metal level, but only where necessary to provide power to the circuit elements. The power antennae are for connecting the power carrying tracks to the circuit elements. Power bridges are disposed in intermediate metal levels between the first metal level and the top metal level. The power bridges are for connecting the power carrying tracks to the power antennae. Contacts to the first metal level are used as a means by which the power antennae are connected to the circuit elements. Vias to the metal levels overlying the first metal level are used as a means by which the power carrying tracks are connected to the power bridges and the power antennae, and by which the power bridges are connected to other power bridges and the power antennae.

Abstract translation: 一种集成电路结构，其采用覆盖电路元件阵列的至少两个金属电平。 每个金属层包含可用于供电和互连电路元件的信号路由资源。 金属水平包括直接覆盖电路元件阵列的第一金属水平，中间金属水平（如果存在多于两个金属水平）以及覆盖所有其它金属水平的顶部金属水平。 电力承载轨道设置在顶部金属水平面上。 功率天线设置在第一金属级，但仅在必要时向电路元件供电。 功率天线用于将电力承载轨道连接到电路元件。 功率桥被布置在第一金属层与顶层金属层之间的中间金属层。 电源桥用于将电力传输轨道连接到电源天线。 与第一金属电平的接触被用作电力天线连接到电路元件的手段。 使用覆盖在第一金属层上的金属层的通路用作电力承载轨道连接到电力桥和功率天线的装置，并且电力桥连接到其它电力桥和功率天线。

公开(公告)号：US4794568A

公开(公告)日：1988-12-27

申请号：US44702

申请日：1987-05-01

Applicant: Hyung-Kyu Lim ,  Jae-Yeong Do ,  Rustam Mehta

Inventor： Hyung-Kyu Lim ,  Jae-Yeong Do ,  Rustam Mehta

IPC: H01L27/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L27/00 ,  G11C7/00

CPC classification number: G11C29/785

Abstract: A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are complementary to the input signals of one of the other program devices. The program of the program devices have two steps to repair the faulty cells. To increase the reliability of redundancy, a nonvolatile memory element used in the program devices is a bridge connected four cell FLOTOX type nonvolatile memory device.

Abstract translation: 正常解码器和具有地址程序设备的冗余解码器用于替换坏小区。 地址编程设备的数量比用于选择正常行或列的输入地址位数多一个。 附加程序设备的输入信号与其他程序设备之一的输入信号互补。 程序设备的程序有两个步骤来修复故障单元。 为了提高冗余的可靠性，在程序设备中使用的非易失性存储元件是连接四个单元FLOTOX型非易失性存储器件的桥。

公开(公告)号：US4038646A

公开(公告)日：1977-07-26

申请号：US666338

申请日：1976-03-12

Applicant: Rustam Mehta ,  Stephen F. Dreyer

Inventor： Rustam Mehta ,  Stephen F. Dreyer

IPC: G11C7/06 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/04

CPC classification number: G11C11/404 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/065

Abstract: An improved dynamic MOS RAM employing capacitive storage memory cells having a single active device per cell. The RAM includes several improved circuits and techniques which reduce power consumption and pattern sensitivity and which also provide a higher speed memory. Complementary input/output lines are employed which are coupled to alternate pair of the bit-sense lines making the use of a bistable output latch and push-pull output buffer more advantageous. The sense amplifiers associated with each of the bit lines are activated by a dual sloped signal to reduce noise and increase sensitivity and gain in the amplifiers. The output lines of the address buffers are initially "high" and then brought to their final level after an address is received by the buffers.