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公开(公告)号：US12105633B2
公开(公告)日：2024-10-01
申请号：US18047791
申请日：2022-10-19
发明人： Qunyi Yang , Yang Jiao , Jin Xiang , Tingli Cui , Xinglin Gui
IPC分类号： G06F12/0862 , G06F12/0882
CPC分类号： G06F12/0882 , G06F12/0862 , G06F2212/7201
摘要： An electronic device is provided. The electronic device includes a memory and an integrated circuit. The integrated circuit includes an address remapping unit. The memory includes multiple memory pages. The integrated circuit converts multiple virtual addresses into multiple physical addresses in sequence. The address remapping unit prefetches a first physical address corresponding to a first virtual address if a second virtual address exceeds a preset offset. The first virtual address is in a different memory page from the second virtual address. The second virtual address is currently processed. The multiple virtual addresses include the first and second virtual addresses.
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公开(公告)号：US12032491B2
公开(公告)日：2024-07-09
申请号：US18047784
申请日：2022-10-19
发明人： Qunyi Yang , Peng Shen , Fan Yang
IPC分类号： G06F12/10 , G06F9/48 , G06F12/1081
CPC分类号： G06F12/1081 , G06F9/4812
摘要： A method for remapping a virtual address to a physical address is provided. The method is used in an address remapping unit and includes: receiving, by a remapping processing unit of the address remapping unit, a remapping request, decoding the remapping request and determining whether the remapping request has a direct memory access (DMA) remapping request; and executing, by the remapping processing unit, a remapping procedure: translating a virtual address corresponding to the remapping request to a physical address, when the remapping request has the DMA remapping request.
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公开(公告)号：US11960427B2
公开(公告)日：2024-04-16
申请号：US17976859
申请日：2022-10-30
发明人： Jingyang Wang , Zhiqiang Hui , Guangyun Wang
IPC分类号： G06F13/362
CPC分类号： G06F13/362
摘要： A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first data storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first data storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second data storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second data storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.
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公开(公告)号：US20240012650A1
公开(公告)日：2024-01-11
申请号：US18472457
申请日：2023-09-22
发明人： Weilin WANG , Yingbing GUAN , Mengchen YANG
CPC分类号： G06F9/30156 , G06F9/3004 , G06F9/223 , G06F9/30189 , G06F9/30174
摘要： A method for executing target instructions and being used in a processor includes the steps of: receiving an instruction; determining whether the received instruction is a target instruction according to an operation code of the received instruction; when the received instruction is not the target instruction, executing the received instruction in a first mode; and when the received instruction is the target instruction, simulating the execution of the target instruction according to basic decoding information of the target instruction in a second mode. The basic decoding information includes the operation code, and is stored in an internal register.
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公开(公告)号：US20230401153A1
公开(公告)日：2023-12-14
申请号：US18308893
申请日：2023-04-28
发明人： Weilin WANG , Yingbing GUAN , Yue QIN
IPC分类号： G06F12/0811 , G06F12/0891 , G06F12/0875
CPC分类号： G06F12/0811 , G06F12/0891 , G06F12/0875 , G06F2212/452
摘要： A processor and a method for designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data are shown. In response to an instruction that is in the instruction set architecture and is executed to designate a designated-level cache within the current core as a target to perform writing-back and invalidation, a decoder of the current core outputs microinstructions. According to the microinstructions, a level-designation request indicating the designated-level cache within the current core is transferred to the hierarchical cache system through the memory order buffer. In response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the current core, writes modified cache lines (which are obtained from the recognized cache lines) back to the system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.
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公开(公告)号：US11761824B2
公开(公告)日：2023-09-19
申请号：US17084997
申请日：2020-10-30
发明人： Shen Li , Zhongding Liu
摘要： A temperature sensing system with simplified wiring comprises an in-core temperature sensing component and an out-of-core temperature-evaluation device. The out-of-core temperature-evaluation device provides a plurality of currents to the in-core temperature sensing module in a time-sharing manner. Corresponding to the plurality of currents, the in-core temperature sensing component generates a plurality of potentials to the out-of-core temperature-evaluation device. The out-of-core temperature-evaluation device evaluates a temperature data by performing a difference calculation on the plurality of potentials.
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公开(公告)号：US11748102B2
公开(公告)日：2023-09-05
申请号：US17471359
申请日：2021-09-10
发明人： Weilin Wang , Mengchen Yang , Yingbing Guan
IPC分类号： G06F9/30 , G06F9/54 , G06F9/38 , G06F9/4401
CPC分类号： G06F9/30145 , G06F9/3861 , G06F9/4411 , G06F9/542
摘要： A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction.
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公开(公告)号：US11681602B2
公开(公告)日：2023-06-20
申请号：US16896216
申请日：2020-06-09
发明人： Lin Li , Xiaoyang Li , Zhiqiang Hui , Zheng Wang , Zongpu Qi
CPC分类号： G06F11/3419 , G06F9/48 , G06F11/3024 , G06F11/3089 , G06F11/3466 , G06F2209/508
摘要： A performance analysis system includes a picker module and a calculation circuit. The picker module is placed in the processing device to capture a plurality of pieces of time information of a unit circuit of each of a plurality of tasks in the processing device during total execution time of processing the plurality of tasks. The calculation circuit performs an interval analysis operation on the time information. The interval analysis operation includes: calculating an overlap period between a current task and a previous task; and counting time occupied by the unit circuit during the total execution time of processing the tasks by the processing device according to a relation between the current time interval of the current task corresponding to the unit circuit and the overlap period.
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公开(公告)号：US20230161709A1
公开(公告)日：2023-05-25
申请号：US18046642
申请日：2022-10-14
发明人： Weilin WANG , Yingbing GUAN , Minfang ZHU
IPC分类号： G06F12/0891 , G06F21/60
CPC分类号： G06F12/0891 , G06F21/602 , G06F2212/1052
摘要： A technology flushing a hierarchical cache structure based on a designated key identification code and a designated address. A processor includes a first core and a last level cache (LLC). The first core includes a decoder, a memory ordering buffer, and a first in-core cache module. In response to an Instruction Set Architecture (ISA) instruction that requests to flush a hierarchical cache structure according to a designated key identification code and a designated address, the decoder outputs at least one microinstruction. According to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then the first in-core cache module provides the LLC with the flushing request, so that the LLC flushes its matching cache line which matches the designated key identification code and the designated address.
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公开(公告)号：US20230128405A1
公开(公告)日：2023-04-27
申请号：US18047791
申请日：2022-10-19
发明人： Qunyi YANG , Yang JIAO , Jin XIANG , Tingli CUI , Xinglin GUI
IPC分类号： G06F12/0882 , G06F12/0862
摘要： An electronic device is provided. The electronic device includes a memory and an integrated circuit. The integrated circuit includes an address remapping unit. The memory includes multiple memory pages. The integrated circuit converts multiple virtual addresses into multiple physical addresses in sequence. The address remapping unit prefetches a first physical address corresponding to a first virtual address if a second virtual address exceeds a preset offset. The first virtual address is in a different memory page from the second virtual address. The second virtual address is currently processed. The multiple virtual addresses include the first and second virtual addresses.
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