公开(公告)号：US07642892B1

公开(公告)日：2010-01-05

申请号：US11373374

申请日：2006-03-10

Applicant: Soon Won Kang

Inventor： Soon Won Kang

IPC: H01C7/00

CPC classification number: H01C7/006 ,  H01C7/022 ,  H01L27/0802 ,  H01L28/24

Abstract: In one aspect, a negative voltage coefficient resistor is provided. The negative voltage coefficient resistor includes an insulative layer positioned between a polycrystalline silicon resistive layer and a silicide layer. Upon application of an appropriate voltage bias at the silicide layer of the resistor, a tunneling current is established across the insulative layer and is supplied to the polycrystalline silicon resistive layer. The tunneling current limits the current flow through the polycrystalline silicon layer, producing a resistor having a negative voltage coefficient of resistance and a reduced temperature coefficient of resistance.

Abstract translation: 一方面，提供负电压系数电阻。 负电压系数电阻器包括位于多晶硅电阻层和硅化物层之间的绝缘层。 当在电阻器的硅化物层处施加适当的电压偏压时，跨越绝缘层建立隧穿电流并提供给多晶硅电阻层。 隧道电流限制了流过多晶硅层的电流，产生具有负的电阻系数和电阻温度系数降低的电阻。

公开(公告)号：US08329533B2

公开(公告)日：2012-12-11

申请号：US12781720

申请日：2010-05-17

Applicant: Julian Chang ,  An-Xing Shen ,  Soon-Won Kang

Inventor： Julian Chang ,  An-Xing Shen ,  Soon-Won Kang

IPC: H01L21/8242

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/60 ,  H01L29/94

Abstract: A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell.

Abstract translation: 提供了一种用于双聚焦闪存的叠层电容器。 堆叠电容器由下电极，下电介质层，中心电极，上电介质层和上电极形成，其中下电极是衬底中的掺杂区域。 该叠层电容器的制造过程可以完全集成到双聚光闪存单元的制造过程中。

公开(公告)号：US20110278656A1

公开(公告)日：2011-11-17

申请号：US12781720

申请日：2010-05-17

Applicant: Julian CHANG ,  An-Xing SHEN ,  Soon-Won KANG

Inventor： Julian CHANG ,  An-Xing SHEN ,  Soon-Won KANG

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/60 ,  H01L29/94

Abstract: A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell.

Abstract translation: 提供了一种用于双聚焦闪存的叠层电容器。 堆叠电容器由下电极，下电介质层，中心电极，上电介质层和上电极形成，其中下电极是衬底中的掺杂区域。 该叠层电容器的制造过程可以完全集成到双聚光闪存单元的制造过程中。