摘要:
A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.
摘要翻译:包括IEEE(Institute of Electrical and Electronics Engineers)1149中规定的TAP控制器和测试访问端口的测试电路包括:第一控制器,包括选择电路和第一TAP控制器,所述选择电路根据TMS产生内部TMS信号 信号并根据选择信号选择内部TMS信号的输出目的地,并且第一TAP控制器基于内部TMS信号改变内部状态,根据用于测试的指令代码来测试相应的测试目标块,并且生成选择 信号,以及第二控制器,包括第二TAP控制器,其基于内部TMS信号改变内部状态,并根据用于测试的指令代码来测试相应的测试目标块。
摘要:
A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as failure information in a failure information storage register. The circuit includes a storage determining circuit determining whether or not to store the failure information in a failure information storage register based on preset failure information storage method information.
摘要:
A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.
摘要:
A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.
摘要翻译:包括IEEE(Institute of Electrical and Electronics Engineers)1149中规定的TAP控制器和测试访问端口的测试电路包括:第一控制器,包括选择电路和第一TAP控制器,所述选择电路根据TMS产生内部TMS信号 信号并根据选择信号选择内部TMS信号的输出目的地,并且第一TAP控制器基于内部TMS信号改变内部状态,根据用于测试的指令代码来测试相应的测试目标块,并且生成选择 信号,以及第二控制器,包括第二TAP控制器,其基于内部TMS信号改变内部状态,并根据用于测试的指令代码来测试相应的测试目标块。
摘要:
A vapor cooling heat exchanger is provided with: a partition wall for partitioning path for a fluid to be cooled through which a fluid to be cooled flows, and path for a refrigerant through which a refrigerant for cooling the fluid to be cooled flows; and fins which are disposed within path for a fluid to be cooled, and which is thermally connected to the partition wall. The fins constitute a first fin and a second fin, the local heat flux of which on the partition wall is smaller than the first fin. The first fin and the second fin are arranged on the basis of the relationship between the local heat flux on the partition wall and the heat flux limit of the refrigerant. As a consequence, the occurrence of local burn-out on the vapor cooling heat exchanger is suppressed.
摘要:
A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as failure information in a failure information storage register. The circuit includes a storage determining circuit determining whether or not to store the failure information in a failure information storage register based on preset failure information storage method information.
摘要:
A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.