公开(公告)号：US10148197B2

公开(公告)日：2018-12-04

申请号：US12865590

申请日：2009-01-21

Applicant: Toshiyuki Maeda ,  Morimitsu Sekimoto ,  Hiroshi Hibino

Inventor： Toshiyuki Maeda ,  Morimitsu Sekimoto ,  Hiroshi Hibino

IPC: H02M7/797 ,  H02M7/5387 ,  H03K17/0814 ,  H02M7/219 ,  H02M1/00

Abstract: An inverter circuit (120) is configured so as to perform synchronous rectification by six switching elements (130). The switching element (130) is formed of an unipolar device (SiC MOSFET in this case) using a wideband gap semiconductor. The inverter circuit (120) uses the body diode (131) of SiC MOSFET (130) as a freewheeling diode during synchronous rectification.

公开(公告)号：US09276516B2

公开(公告)日：2016-03-01

申请号：US13643134

申请日：2011-04-28

Applicant: Yoshiyuki Harada ,  Toshiyuki Maeda

Inventor： Yoshiyuki Harada ,  Toshiyuki Maeda

IPC: H02M1/32 ,  H02P27/08 ,  F25B31/00 ,  H02P29/00 ,  H02M1/44 ,  F25B49/02

CPC classification number: H02P27/08 ,  F25B13/00 ,  F25B31/006 ,  F25B49/025 ,  F25B2313/003 ,  F25B2313/021 ,  F25B2600/021 ,  F25B2600/024 ,  H02M1/44 ,  H02M2001/327 ,  H02P29/68 ,  Y02B30/741

Abstract: A refrigeration apparatus includes a refrigerant circuit with a compressor, a power module, a refrigerant cooler in contact with the power module, and an IPM motor which drives the compressor. A refrigerant in the refrigerant circuit flows through the refrigerant cooler, and cooling of the power module is performed by dissipating heat to the refrigerant flowing in the refrigerant cooler. A controller in the refrigeration apparatus outputs a driving signal to a drive circuit to reduce the number of switching operations of switching elements by performing overmodulation control such that there exists a carrier cycle in which no switching is performed.

Abstract translation: 制冷装置包括具有压缩机的制冷剂回路，功率模块，与功率模块接触的制冷剂冷却器，以及驱动压缩机的IPM电动机。 制冷剂回路中的制冷剂流过制冷剂冷却器，通过向在制冷剂冷却器中流动的制冷剂散热而进行动力组件的冷却。 制冷装置中的控制器通过执行过调制控制将驱动信号输出到驱动电路来减少开关元件的开关操作次数，使得存在不进行开关的载波周期。

公开(公告)号：US09257931B2

公开(公告)日：2016-02-09

申请号：US13980285

申请日：2012-01-18

Applicant: Eiji Tooyama ,  Morimitsu Sekimoto ,  Toshiyuki Maeda

Inventor： Eiji Tooyama ,  Morimitsu Sekimoto ,  Toshiyuki Maeda

IPC: H02P6/00 ,  H02J1/00 ,  H02P23/00 ,  H02M1/12 ,  H02P21/05

CPC classification number: H02P23/0095 ,  H02M1/12 ,  H02P21/05 ,  H02P29/50

Abstract: A power conversion apparatus is equipped with switching devices to perform power conversion of input AC power supplied from an AC power supply to output AC power having a predetermined voltage and a predetermined frequency, and to supply the power to a motor connected thereto. The apparatus includes a controller controlling switching of the switching devices, a capacitor smoothing a ripple generated by the switching of the switching devices, a current controller controlling a current flowing to the motor, and a voltage distortion corrector detecting a harmonic component caused by distortion in motor input power, and superimposing compensation values on an output of the current controller in accordance with a value of the harmonic component.

Abstract translation: 电力转换装置配备有开关装置，对从交流电源供给的输入交流电力进行电力转换，输出具有预定电压和预定频率的交流电力，并向与其连接的电动机供电。 该装置包括控制切换装置的切换的控制器，平滑由切换装置的切换产生的纹波的电容器，控制流向马达的电流的电流控制器，以及检测由失真引起的谐波成分的电压失真校正器 马达输入功率，并根据谐波分量的值将补偿值叠加在电流控制器的输出上。

公开(公告)号：US20130300334A1

公开(公告)日：2013-11-14

申请号：US13980285

申请日：2012-01-18

Applicant: Eiji Tooyama ,  Morimitsu Sekimoto ,  Toshiyuki Maeda

Inventor： Eiji Tooyama ,  Morimitsu Sekimoto ,  Toshiyuki Maeda

IPC: H02P23/00

CPC classification number: H02P23/0095 ,  H02M1/12 ,  H02P21/05 ,  H02P29/50

Abstract: A power conversion apparatus is equipped with switching devices to perform power conversion of input AC power supplied from an AC power supply to output AC power having a predetermined voltage and a predetermined frequency, and to supply the power to a motor connected thereto. The apparatus includes a controller controlling switching of the switching devices, a capacitor smoothing a ripple generated by the switching of the switching devices, a current controller controlling a current flowing to the motor, and a voltage distortion corrector detecting a harmonic component caused by distortion in motor input power, and superimposing compensation values on an output of the current controller in accordance with a value of the harmonic component.

Abstract translation: 电力转换装置配备有开关装置，对从交流电源供给的输入交流电力进行电力转换，输出具有预定电压和预定频率的交流电力，并向与其连接的电动机供电。 该装置包括控制切换装置的切换的控制器，平滑由切换装置的切换产生的纹波的电容器，控制流向马达的电流的电流控制器，以及检测由失真引起的谐波成分的电压失真校正器 马达输入功率，并根据谐波分量的值将补偿值叠加在电流控制器的输出上。

公开(公告)号：US20120182770A1

公开(公告)日：2012-07-19

申请号：US13498444

申请日：2010-09-28

Applicant: Morimitsu Sekimoto ,  Hiroshi Hibino ,  Tomoisa Taniguchi ,  Toshiyuki Maeda

Inventor： Morimitsu Sekimoto ,  Hiroshi Hibino ,  Tomoisa Taniguchi ,  Toshiyuki Maeda

IPC: H02M5/458

CPC classification number: H02M7/53873 ,  H02M1/126

Abstract: The power converter includes a diode rectifier which rectifies alternating current power output from an alternating current power supply, a reactor provided between the alternating current power supply and the diode rectifier, an inverter circuit to which power output from the diode rectifier is directly supplied, and a capacitor provided between power supply lines on a primary side of the diode rectifier.

Abstract translation: 电力转换器包括：二极管整流器，对来自交流电源的交流电力输出，设置在交流电源和二极管整流器之间的电抗器进行整流;逆变器电路，直接从二极管整流器输出的功率;以及 在二极管整流器的初级侧的电源线之间设置电容器。

公开(公告)号：US08199072B2

公开(公告)日：2012-06-12

申请号：US12513687

申请日：2007-12-07

Applicant: Toshiyuki Maeda ,  Hidehiko Shoji

Inventor： Toshiyuki Maeda ,  Hidehiko Shoji

IPC: G09G3/28

CPC classification number: G09G3/2965 ,  G09G3/2927 ,  G09G2310/066

Abstract: A scan electrode driving circuit applies a rising ramp waveform voltage to scan electrodes (SCN1 to SCNn) to generate a first setup discharge in a first period within a setup period, applies a dropping ramp waveform voltage to the scan electrodes (SCN1 to SCNn) to generate a second setup discharge in a second period following the first period within the setup period, and applies a first positive rectangular waveform voltage (Vs), a negative rectangular waveform voltage (Va), a second positive rectangular waveform voltage (Vs) and a dropping ramp waveform voltage to the scan electrodes (SCN1 to SCNn) in a third period following the second period within the setup period. A data electrode driving circuit applies a positive rectangular waveform voltage (Vd) to data electrodes (D1 to Dm) in a period after application of the first positive rectangular waveform voltage (Vs) to the scan electrodes (SCN1 to SCNn) and before application of the negative rectangular waveform voltage (Va) to the scan electrodes (SCN1 to SCNn) in the third period.

Abstract translation: 扫描电极驱动电路向扫描电极（SCN1〜SCNn）施加上升斜坡波形电压，以在初始化期间内的第一期间产生第一次建立放电，向扫描电极（SCN1〜SCNn）施加下降斜坡波形电压至 在建立周期内的第一周期之后的第二周期中产生第二设定放电，并施加第一正矩形波形电压（Vs），负矩形波形电压（Va），第二正矩形波形电压（Vs）和 在设定期间内的第二期间之后的第三期间，向扫描电极（SCN1〜SCNn）施加斜坡波形电压。 数据电极驱动电路在对扫描电极（SCN1〜SCNn）施加第一正矩形波形电压（Vs）之后的期间内施加正的矩形波形电压（Vd）至数据电极（D1〜Dm） 在第三周期中对扫描电极（SCN1〜SCNn）的负矩形波形电压（Va）。

公开(公告)号：US08056036B2

公开(公告)日：2011-11-08

申请号：US12153596

申请日：2008-05-21

Applicant: Toshiyuki Maeda ,  Toshiharu Asaka

Inventor： Toshiyuki Maeda ,  Toshiharu Asaka

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G01R31/318583

Abstract: A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.

Abstract translation: 一种基于TPI技术设计半导体集成电路的方法，包括：（A）从包括在设计电路中的多个节点中选择目标节点; （B）在目标节点插入一个测试点; （C）指定相对于连接到测试点的路径的测试点路径的延迟时间; 和（D）布置设计电路，使得测试点路径的延迟时间变为指定的延迟时间。 （A）选择包括：（A1）计算相对于所述多个节点中的每一个的扇入路径和扇出路径的延迟时间; 和（A2）基于所计算的延迟时间从多个节点中选择目标节点。

公开(公告)号：US20110175638A1

公开(公告)日：2011-07-21

申请号：US13007366

申请日：2011-01-14

Applicant: Toshiyuki MAEDA

Inventor： Toshiyuki MAEDA

IPC: G01R31/26

CPC classification number: G01R31/318558 ,  G01R31/318563

Abstract: A semiconductor circuit inhibiting the increase in the number of elements required to enable core circuit testing and a core test circuit enabling consecutive-pattern testing of a core circuit without increasing the number of terminals are provided. The semiconductor circuit includes a core circuit, a combinational circuit, a scan path for the combinational circuit with the scan path including cascaded scan flip-flops connected to input and output terminals of the combinational circuit, and scan path sharing circuits including multiplexers for allowing output signals of the core circuit to be inputted to the scan flip-flops, and allows a core circuit not included in the combinational circuit to be tested using the scan path for the combinational circuit. The core test circuit is provided with output shift registers for storing and outputting test results of plural test patterns outputted from output terminals of the core circuit to be eventually scanned out from the output shift registers.

Abstract translation: 提供一种半导体电路，其抑制使核心电路测试所需要的元件数量的增加以及能够不增加端子数量而实现核心电路的连续图案测试的核心测试电路。 半导体电路包括核心电路，组合电路，组合电路的扫描路径，扫描路径包括连接到组合电路的输入和输出端子的级联扫描触发器，以及扫描路径共享电路，包括用于允许输出的多路复用器 要被输入到扫描触发器的核心电路的信号，并且允许不包括在组合电路中的核心电路使用用于组合电路的扫描路径进行测试。 核心测试电路设置有输出移位寄存器，用于存储并输出从输出移位寄存器最终扫描的核心电路的输出端输出的多个测试模式的测试结果。

公开(公告)号：US07821950B2

公开(公告)日：2010-10-26

申请号：US12219586

申请日：2008-07-24

Applicant: Junji Murata ,  Toshiyuki Maeda ,  Toshihiro Hakata

Inventor： Junji Murata ,  Toshiyuki Maeda ,  Toshihiro Hakata

IPC: G06F11/00

CPC classification number: G01M13/045

Abstract: In an evaluation apparatus of a hub unit, a signal processing unit outputs frequency analysis signals which indicate such a result obtained by that an output signal of an acceleration sensor fixed on a hub unit by a magnet is processed via an A/D converting unit and an envelope detecting unit, and thereafter, the processed sensor signal is analyzed for a frequency analysis by an FFT unit. Then, an evaluation output unit evaluates damage conditions of the hub unit based upon signal strengths of specific frequencies, and overall values, which are acquired from the frequency analysis signals, and then, outputs the evaluated damage condition to a display unit.

Abstract translation: 在集线器单元的评估装置中，信号处理单元输出表示通过A / D转换单元处理通过磁体固定在集线器单元上的加速度传感器的输出信号得到的结果的频率分析信号， 包络检测单元，此后，对经处理的传感器信号进行FFT单元的频率分析。 然后，评价输出单元基于特定频率的信号强度和从频率分析信号获取的总体值来评估集线器单元的损坏状况，然后将评估的损坏状况输出到显示单元。

公开(公告)号：US20100259521A1

公开(公告)日：2010-10-14

申请号：US12747003

申请日：2008-09-04

Applicant: Toshiyuki Maeda ,  Kenji Ogawa ,  Naoki Noguchi ,  Takahiko Origuchi

Inventor： Toshiyuki Maeda ,  Kenji Ogawa ,  Naoki Noguchi ,  Takahiko Origuchi

IPC: G09G3/28 ,  G09G5/00

CPC classification number: G09G3/293 ,  G09G3/2925 ,  G09G2320/0228 ,  G09G2360/16

Abstract: A two-phase driving operation is performed by a first circuit and a second circuit in at least one sub-field. The first circuit applies a first ramp waveform that drops from a first potential to a second potential to a plurality of first scan electrodes in a setup period, and sequentially applies a scan pulse to the plurality of first scan electrodes in a write period. The second circuit applies a second ramp waveform that drops from the first potential to a third potential that is higher than the second potential to a plurality of second scan electrodes, and then raises the plurality of second scan electrodes to a fourth potential in the setup period, and holds the plurality of second scan electrodes at a fifth potential that is higher than the third potential and lower than the fourth potential in a period where the first scan pulse is applied, and then sequentially applies a scan pulse to the plurality of second electrodes in the write period. Discharge failures during write discharges can be prevented from occurring by employing the two-phase driving operation.

Abstract translation: 在至少一个子场中由第一电路和第二电路执行两相驱动操作。 第一电路在初始化周期中施加从第一电位降低到第二电位的第一斜坡波形，并且在写入周期中顺序地对多个第一扫描电极施加扫描脉冲。 第二电路对第一扫描电极施加从第一电位下降到高于第二电位的第三电位的第二斜坡波形，然后在初始化周期中将多个第二扫描电极升高到第四电位 并且在施加第一扫描脉冲的周期中将多个第二扫描电极保持在高于第三电位且低于第四电位的第五电位，然后顺序地将多个第二电极施加扫描脉冲 在写期间。 可以通过采用两相驱动操作来防止写放电期间的放电故障。