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公开(公告)号：US20080281547A1
公开(公告)日：2008-11-13
申请号：US12149742
申请日：2008-05-07
IPC分类号： G01R31/317
CPC分类号： G01R31/31855
摘要： A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.
摘要翻译： 包括IEEE（Institute of Electrical and Electronics Engineers）1149中规定的TAP控制器和测试访问端口的测试电路包括：第一控制器，包括选择电路和第一TAP控制器，所述选择电路根据TMS产生内部TMS信号 信号并根据选择信号选择内部TMS信号的输出目的地，并且第一TAP控制器基于内部TMS信号改变内部状态，根据用于测试的指令代码来测试相应的测试目标块，并且生成选择 信号，以及第二控制器，包括第二TAP控制器，其基于内部TMS信号改变内部状态，并根据用于测试的指令代码来测试相应的测试目标块。
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公开(公告)号：US08015462B2
公开(公告)日：2011-09-06
申请号：US12149742
申请日：2008-05-07
IPC分类号： G01R31/28
CPC分类号： G01R31/31855
摘要： A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.
摘要翻译： 包括IEEE（Institute of Electrical and Electronics Engineers）1149中规定的TAP控制器和测试访问端口的测试电路包括：第一控制器，包括选择电路和第一TAP控制器，所述选择电路根据TMS产生内部TMS信号 信号并根据选择信号选择内部TMS信号的输出目的地，并且第一TAP控制器基于内部TMS信号改变内部状态，根据用于测试的指令代码来测试相应的测试目标块，并且生成选择 信号，以及第二控制器，包括第二TAP控制器，其基于内部TMS信号改变内部状态，并根据用于测试的指令代码来测试相应的测试目标块。
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3.发明申请Semiconductor integrated circuit, BIST circuit, design program of BIST circuit, design device of BIST circuit and test method of memory 有权半导体集成电路，BIST电路，BIST电路设计程序，BIST电路设计器件和存储器测试方法公开(公告)号：US20080077831A1
公开(公告)日：2008-03-27
申请号：US11902830
申请日：2007-09-26
IPC分类号： G11C29/18
CPC分类号： G11C29/16 , G11C29/10 , G11C29/18 , G11C2029/0405 , G11C2029/3602
摘要： A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.
摘要翻译： 半导体集成电路包括存储器，BIST主电路和BIST子电路。 BIST子电路是生成存储器的行地址模式或列地址模式，并且包括边界地址生成电路，用于交替地生成行地址模式和行地址模式中的至少一个的存储器的顶部地址和底部地址 列地址模式。 BIST主电路与多个存储器共同提供，并且BIST子电路对应于存储器单独提供。 边界地址生成电路包括用于存储顶部地址的顶部地址存储单元和用于读出顶部地址的顶部/底部地址生成单元，并交替地输出顶部地址和底部地址。
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4.发明授权Semiconductor integrated circuit, BIST circuit, design program of BIST circuit, design device of BIST circuit and test method of memory 有权半导体集成电路，BIST电路，BIST电路设计程序，BIST电路设计器件和存储器测试方法公开(公告)号：US07681096B2
公开(公告)日：2010-03-16
申请号：US11902830
申请日：2007-09-26
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/10 , G11C29/18 , G11C2029/0405 , G11C2029/3602
摘要： A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.
摘要翻译： 半导体集成电路包括存储器，BIST主电路和BIST子电路。 BIST子电路是生成存储器的行地址模式或列地址模式，并且包括边界地址生成电路，用于交替地生成行地址模式和行地址模式中的至少一个的存储器的顶部地址和底部地址 列地址模式。 BIST主电路与多个存储器共同提供，并且BIST子电路对应于存储器单独提供。 边界地址生成电路包括用于存储顶部地址的顶部地址存储单元和用于读出顶部地址的顶部/底部地址生成单元，并交替地输出顶部地址和底部地址。
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5.发明申请Method of designing semiconductor integrated circuit using test point insertion adjustable to delay time 审中-公开使用测试点插入设计半导体集成电路的方法可调节延迟时间公开(公告)号：US20080148209A1
公开(公告)日：2008-06-19
申请号：US12000429
申请日：2007-12-12
申请人： Toshiyuki Maeda , Toshiharu Asaka
发明人： Toshiyuki Maeda , Toshiharu Asaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/3016
摘要： A method of designing a semiconductor integrated circuit is based on a TPI (Test Point Insertion) technique. The design method includes: inserting a test point into a target node in a designed circuit and designating delay time for a test point path connected to the test point. Thereafter, a layout of a designed circuit is made so that delay time of the test point path becomes the above described designated delay time.
摘要翻译： 设计半导体集成电路的方法是基于TPI（测试点插入）技术。 该设计方法包括：将测试点插入设计电路中的目标节点，并指定连接到测试点的测试点路径的延迟时间。 此后，设计电路的布局使得测试点路径的延迟时间变为上述指定的延迟时间。
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6.发明授权Semiconductor integrated circuit and method of designing thereof based on TPI 有权半导体集成电路及其基于TPI的设计方法公开(公告)号：US08056036B2
公开(公告)日：2011-11-08
申请号：US12153596
申请日：2008-05-21
申请人： Toshiyuki Maeda , Toshiharu Asaka
发明人： Toshiyuki Maeda , Toshiharu Asaka
CPC分类号： G01R31/318583
摘要： A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.
摘要翻译： 一种基于TPI技术设计半导体集成电路的方法，包括：（A）从包括在设计电路中的多个节点中选择目标节点; （B）在目标节点插入一个测试点; （C）指定相对于连接到测试点的路径的测试点路径的延迟时间; 和（D）布置设计电路，使得测试点路径的延迟时间变为指定的延迟时间。 （A）选择包括：（A1）计算相对于所述多个节点中的每一个的扇入路径和扇出路径的延迟时间; 和（A2）基于所计算的延迟时间从多个节点中选择目标节点。
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7.发明申请Semiconductor integrated circuit and method of designing thereof based on TPI 有权半导体集成电路及其基于TPI的设计方法公开(公告)号：US20080295050A1
公开(公告)日：2008-11-27
申请号：US12153596
申请日：2008-05-21
申请人： Toshiyuki Maeda , Toshiharu Asaka
发明人： Toshiyuki Maeda , Toshiharu Asaka
IPC分类号： G06F17/50
CPC分类号： G01R31/318583
摘要： A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.
摘要翻译： 一种基于TPI技术设计半导体集成电路的方法，包括：（A）从包括在设计电路中的多个节点中选择目标节点; （B）在目标节点插入一个测试点; （C）指定相对于连接到测试点的路径的测试点路径的延迟时间; 和（D）布置设计电路，使得测试点路径的延迟时间变为指定的延迟时间。 （A）选择包括：（A1）计算相对于所述多个节点中的每一个的扇入路径和扇出路径的延迟时间; 和（A2）基于所计算的延迟时间从多个节点中选择目标节点。
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8.发明授权Logic synthesis for testability system which enables improvement in testability and effective selection of center state and logic synthesis method thereof 失效用于可测试性系统的逻辑合成，其能够改善中心状态的可测试性和有效选择及其逻辑合成方法
公开(公告)号：US6070258A
公开(公告)日：2000-05-30
申请号：US35816
申请日：1998-03-06
申请人： Toshiharu Asaka
发明人： Toshiharu Asaka
IPC分类号： G06F17/50 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318583
摘要： A logic synthesis for testability system including a testability improving unit which employs a center state of an FSM of a circuit as a target for logic synthesis to reduce a distance between predetermined states for improving testability of the circuit expressed by the FSM which is held in a storage unit, the testability improving unit including a center state candidate selecting unit for excluding an asynchronous reset state and a predetermined state with a short distance from the asynchronous reset state from center state candidates and a center state selecting unit for sequentially selecting states not excluded by the center state candidate selecting unit as center state candidates, thereby conducting optimization processing taking testability into consideration during logic circuit designing.
摘要翻译： 一种用于可测试性系统的逻辑综合，其包括可测试性改进单元，其采用电路的FSM的中心状态作为用于逻辑合成的目标，以减小预定状态之间的距离，以提高由FSM表示的电路的可测试性 存储单元，所述可测试性改进单元包括用于排除异步复位状态的中心状态候选选择单元和与所述异步复位状态距离中心状态候选的距离短的预定状态;以及中心状态选择单元，用于顺序地选择不被所述异步复位状态排除的状态 中心状态候选选择单元作为中心状态候选，从而在逻辑电路设计期间进行考虑可测性的优化处理。
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公开(公告)号：US5721690A
公开(公告)日：1998-02-24
申请号：US516549
申请日：1995-08-18
申请人： Toshiharu Asaka
发明人： Toshiharu Asaka
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for a logic optimization in a logic synthesis comprises the following steps. Prior to an actual execution of a logic flattening process, a scale of unoptimized circuits is estimated assuming that the unoptimized circuits have already been subjected to the logical flattening. The unoptimized circuits are subjected to a two-level logic optimization only when an estimated scale of the unoptimized circuits exceeds a predetermined threshold value. Prior to an actual execution of a logic flattening process, a scale of the optimized circuits is estimated assuming that the optimized circuits have already been subjected to the logic flattening. The optimized circuits are subjected to the logic flattening if an estimated scale of the optimized circuits does not exceed the predetermined threshold value.
摘要翻译： 逻辑合成中逻辑优化的方法包括以下步骤。 在实际执行逻辑平坦化处理之前，假设未优化的电路已经经历了逻辑平坦化，估计未优化电路的规模。 仅当非优化电路的估计标度超过预定阈值时，未优化电路才进行两级逻辑优化。 在实际执行逻辑平坦化处理之前，假设优化的电路已经经历了逻辑平坦化，估计了优化电路的规模。 如果优化电路的估计比例不超过预定阈值，则优化的电路经受逻辑平坦化。
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公开(公告)号：US20060179376A1
公开(公告)日：2006-08-10
申请号：US11348414
申请日：2006-02-07
申请人： Toshiharu Asaka
发明人： Toshiharu Asaka
IPC分类号： G01R31/28
CPC分类号： G01R31/31858
摘要： A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.
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