公开(公告)号：US20080281547A1

公开(公告)日：2008-11-13

申请号：US12149742

申请日：2008-05-07

申请人： Yoshiyuki Nakamura ,  Toshiharu Asaka ,  Toshiyuki Maeda ,  Tomonori Sasaki

发明人： Yoshiyuki Nakamura ,  Toshiharu Asaka ,  Toshiyuki Maeda ,  Tomonori Sasaki

IPC分类号： G01R31/317

CPC分类号： G01R31/31855

摘要： A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.

摘要翻译： 包括IEEE（Institute of Electrical and Electronics Engineers）1149中规定的TAP控制器和测试访问端口的测试电路包括：第一控制器，包括选择电路和第一TAP控制器，所述选择电路根据TMS产生内部TMS信号 信号并根据选择信号选择内部TMS信号的输出目的地，并且第一TAP控制器基于内部TMS信号改变内部状态，根据用于测试的指令代码来测试相应的测试目标块，并且生成选择 信号，以及第二控制器，包括第二TAP控制器，其基于内部TMS信号改变内部状态，并根据用于测试的指令代码来测试相应的测试目标块。

公开(公告)号：US07603595B2

公开(公告)日：2009-10-13

申请号：US11642898

申请日：2006-12-21

申请人： Tomonori Sasaki

发明人： Tomonori Sasaki

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C2029/0405

摘要： A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as failure information in a failure information storage register. The circuit includes a storage determining circuit determining whether or not to store the failure information in a failure information storage register based on preset failure information storage method information.

摘要翻译： 根据本发明的实施例的存储器测试电路根据指定测试图案中包括的子测试图案的模式模式信号对存储器执行测试，并且包括用于存储器的多个测试动作，并且存储模式 模式信号作为故障信息存储寄存器中的故障信息。 该电路包括存储确定电路，其基于预设的故障信息存储方法信息来确定是否将故障信息存储在故障信息存储寄存器中。

公开(公告)号：US20080077831A1

公开(公告)日：2008-03-27

申请号：US11902830

申请日：2007-09-26

申请人： Tomonori Sasaki ,  Toshiharu Asaka ,  Yoshiyuki Nakamura

发明人： Tomonori Sasaki ,  Toshiharu Asaka ,  Yoshiyuki Nakamura

IPC分类号： G11C29/18

CPC分类号： G11C29/16 ,  G11C29/10 ,  G11C29/18 ,  G11C2029/0405 ,  G11C2029/3602

摘要： A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

摘要翻译： 半导体集成电路包括存储器，BIST主电路和BIST子电路。 BIST子电路是生成存储器的行地址模式或列地址模式，并且包括边界地址生成电路，用于交替地生成行地址模式和行地址模式中的至少一个的存储器的顶部地址和底部地址 列地址模式。 BIST主电路与多个存储器共同提供，并且BIST子电路对应于存储器单独提供。 边界地址生成电路包括用于存储顶部地址的顶部地址存储单元和用于读出顶部地址的顶部/底部地址生成单元，并交替地输出顶部地址和底部地址。

公开(公告)号：US08015462B2

公开(公告)日：2011-09-06

申请号：US12149742

申请日：2008-05-07

申请人： Yoshiyuki Nakamura ,  Toshiharu Asaka ,  Toshiyuki Maeda ,  Tomonori Sasaki

发明人： Yoshiyuki Nakamura ,  Toshiharu Asaka ,  Toshiyuki Maeda ,  Tomonori Sasaki

IPC分类号： G01R31/28

CPC分类号： G01R31/31855

摘要： A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.

摘要翻译： 包括IEEE（Institute of Electrical and Electronics Engineers）1149中规定的TAP控制器和测试访问端口的测试电路包括：第一控制器，包括选择电路和第一TAP控制器，所述选择电路根据TMS产生内部TMS信号 信号并根据选择信号选择内部TMS信号的输出目的地，并且第一TAP控制器基于内部TMS信号改变内部状态，根据用于测试的指令代码来测试相应的测试目标块，并且生成选择 信号，以及第二控制器，包括第二TAP控制器，其基于内部TMS信号改变内部状态，并根据用于测试的指令代码来测试相应的测试目标块。

公开(公告)号：US20120211215A1

公开(公告)日：2012-08-23

申请号：US13504562

申请日：2010-11-05

申请人： Fumihiko Ishiguro ,  Hirohisa Kato ,  Mitsuru Kubo ,  Tomonori Sasaki ,  Yuichiro Tomono

发明人： Fumihiko Ishiguro ,  Hirohisa Kato ,  Mitsuru Kubo ,  Tomonori Sasaki ,  Yuichiro Tomono

IPC分类号： F28F7/00

CPC分类号： F28D9/0062 ,  F28F13/14

摘要： A vapor cooling heat exchanger is provided with: a partition wall for partitioning path for a fluid to be cooled through which a fluid to be cooled flows, and path for a refrigerant through which a refrigerant for cooling the fluid to be cooled flows; and fins which are disposed within path for a fluid to be cooled, and which is thermally connected to the partition wall. The fins constitute a first fin and a second fin, the local heat flux of which on the partition wall is smaller than the first fin. The first fin and the second fin are arranged on the basis of the relationship between the local heat flux on the partition wall and the heat flux limit of the refrigerant. As a consequence, the occurrence of local burn-out on the vapor cooling heat exchanger is suppressed.

摘要翻译： 蒸汽冷却热交换器具有：待冷却流体流过的待冷却流体的分隔路径的分隔壁和用于冷却待冷却流体的制冷剂流过的制冷剂通路， 以及翅片，其设置在待冷却流体的路径内，并且热连接到分隔壁。 翅片构成第一翅片和第二翅片，其间隔壁的局部热通量小于第一翅片。 第一翅片和第二翅片基于隔壁上的局部热通量与制冷剂的热通量极限之间的关系来布置。 结果，抑制了在蒸气冷却热交换器上发生局部烧坏。

公开(公告)号：US20070150777A1

公开(公告)日：2007-06-28

申请号：US11642898

申请日：2006-12-21

申请人： Tomonori Sasaki

发明人： Tomonori Sasaki

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C2029/0405

摘要： A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as failure information in a failure information storage register. The circuit includes a storage determining circuit determining whether or not to store the failure information in a failure information storage register based on preset failure information storage method information.

摘要翻译： 根据本发明的实施例的存储器测试电路根据指定测试图案中包括的子测试图案的模式模式信号对存储器执行测试，并且包括用于存储器的多个测试动作，并且存储模式 模式信号作为故障信息存储寄存器中的故障信息。 该电路包括存储确定电路，其基于预设的故障信息存储方法信息来确定是否将故障信息存储在故障信息存储寄存器中。

公开(公告)号：US07681096B2

公开(公告)日：2010-03-16

申请号：US11902830

申请日：2007-09-26

申请人： Tomonori Sasaki ,  Toshiharu Asaka ,  Yoshiyuki Nakamura

发明人： Tomonori Sasaki ,  Toshiharu Asaka ,  Yoshiyuki Nakamura

IPC分类号： G11C29/00

CPC分类号： G11C29/16 ,  G11C29/10 ,  G11C29/18 ,  G11C2029/0405 ,  G11C2029/3602

摘要： A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

摘要翻译： 半导体集成电路包括存储器，BIST主电路和BIST子电路。 BIST子电路是生成存储器的行地址模式或列地址模式，并且包括边界地址生成电路，用于交替地生成行地址模式和行地址模式中的至少一个的存储器的顶部地址和底部地址 列地址模式。 BIST主电路与多个存储器共同提供，并且BIST子电路对应于存储器单独提供。 边界地址生成电路包括用于存储顶部地址的顶部地址存储单元和用于读出顶部地址的顶部/底部地址生成单元，并交替地输出顶部地址和底部地址。