公开(公告)号：US08524558B2

公开(公告)日：2013-09-03

申请号：US13200882

申请日：2011-10-04

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

公开(公告)号：US08058687B2

公开(公告)日：2011-11-15

申请号：US11700688

申请日：2007-01-30

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

公开(公告)号：US08022482B2

公开(公告)日：2011-09-20

申请号：US11355128

申请日：2006-02-14

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L21/08 ,  H01L27/088 ,  H01L29/40 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/812

CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/1082

摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. In a preferred embodiment, the semiconductor power device constitutes an asymmetrical double diffusion metal oxide semiconductor field effect transistor (DMOSFET) device.

摘要翻译： 沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。 围绕沟槽栅极的源极区域包括具有低势垒高度的金属，用作肖特基源。 低阻挡高度的金属还可以包括PtSi或ErSi层。 在优选实施例中，低势垒高度的金属还包括ErSi层。 低势垒高度的金属还可以是具有低势垒高度的金属硅化物层。 顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。 源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。 在优选实施例中，半导体功率器件构成非对称双扩散金属氧化物半导体场效应晶体管（DMOSFET）器件。

公开(公告)号：US20080179668A1

公开(公告)日：2008-07-31

申请号：US11700688

申请日：2007-01-30

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

公开(公告)号：US20070281418A1

公开(公告)日：2007-12-06

申请号：US11444852

申请日：2006-05-31

申请人： YongZhong Hu ,  Sung-Shan Tai

发明人： YongZhong Hu ,  Sung-Shan Tai

IPC分类号： H01L21/8244

CPC分类号： H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  Y10S438/957

摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

摘要翻译： 半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层 从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。 虽然高片rho电阻也形成在同一个多晶硅层上，多晶硅层的差分掺杂。

公开(公告)号：US20070069297A1

公开(公告)日：2007-03-29

申请号：US11541369

申请日：2006-09-30

申请人： YongZhong Hu ,  Yu Chang ,  Sung-Shan Tai

发明人： YongZhong Hu ,  Yu Chang ,  Sung-Shan Tai

IPC分类号： H01L23/62

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/11206

摘要： A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.

摘要翻译： 在本发明中公开了执行编程，测试和修整操作的方法。 该方法包括应用用于对OTP存储器进行编程的编程电路的步骤，用于探测和感测OTP存储器的三种不同状态之一，以使用OTP存储器的三种状态之一进行修整操作，由此OTP的较高利用率 实现了存储单元。 将OTP的两个导电电路选择和编程成两个不同的操作特性，因此能够存储和感测OTP存储器的三种不同状态之一。 这两个导电电路可以包括用于编程成线性电阻器的两个不同晶体管和具有不同电流传导特性的非线性电阻器。 编程过程包括应用高电压和不同的编程电流，从而产生这两个晶体管的不同操作特性。

公开(公告)号：US06842372B1

公开(公告)日：2005-01-11

申请号：US10236829

申请日：2002-09-06

申请人： YongZhong Hu

发明人： YongZhong Hu

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11558

摘要： An EEPROM memory device includes a substrate of a first conductivity type having a cell well region of a second conductivity type therein. A floating-gate transistor of the first conductivity type resides in the cell well region and includes a first region separated from a second region by a channel region. A write transistor of the second conductivity type resides in the substrate and includes a first region separated from a second region by a channel region. The second region partially extends into the cell well region and forms a p-n junction with the second region of the floating-gate transistor. The process for fabricating the EEPROM device includes forming the cell well region in the substrate by creating a retrograde doping profile. In operation, the EEPROM device transfers electrons between the cell well region and the floating-gate electrode during both programming and erasing operations.

摘要翻译： EEPROM存储器件包括其中具有第二导电类型的单元阱区的第一导电类型的衬底。 第一导电类型的浮栅晶体管位于电池阱区中，并且包括通过沟道区与第二区分离的第一区。 第二导电类型的写入晶体管位于衬底中，并且包括通过沟道区域与第二区域分离的第一区域。 第二区域部分地延伸到电池阱区域中，并与浮栅晶体管的第二区域形成p-n结。 制造EEPROM器件的工艺包括通过产生逆向掺杂分布形成衬底中的电池阱区域。 在操作中，EEPROM器件在编程和擦除操作期间在电池阱区域和浮栅电极之间传送电子。

公开(公告)号：US06306713B1

公开(公告)日：2001-10-23

申请号：US09799469

申请日：2001-03-05

申请人： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Hiroyuki Kinoshita

发明人： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Hiroyuki Kinoshita

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L2924/3011

摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers. The multi-layer structures and the source and drain regions are silicided and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A photoresist contact mask is deposited, processed, and used to form core contact openings over the core region, which expose the multi-layer structure in addition to the source and drain regions while covering the peripheral region. Protective secondary sidewall spacers are formed in the core contact openings over the exposed multi-layer structures. A second photoresist contact mask is deposited, processed, and used to form peripheral local interconnect openings over the peripheral region which the source and drain regions and portions of the plurality of multi-layer structures in the peripheral region while covering the core region. A conductive material is deposited over the dielectric layer and in the core contact and peripheral local interconnect openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings.

摘要翻译： 提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。 围绕多层结构形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入。 多层结构和源极和漏极区域被硅化，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。 光致抗蚀剂接触掩模被沉积，加工并用于在芯部区域上形成芯接触开口，除了覆盖周边区域之外，还暴露多层结构以及源极和漏极区域。 保护性次级侧壁间隔件形成在暴露的多层结构上的芯接触开口中。 第二光致抗蚀剂接触掩模被沉积，加工并用于在外围区域上形成周边局部互连开口，周边区域是外围区域的源极和漏极区域以及多个多层结构的部分，同时覆盖芯部区域。 导电材料沉积在电介质层上，并在芯接触和外围局部互连开口中沉积，并进行化学机械平面化以去除电介质层上的导电材料，使得导电材料在芯和外围接触开口中被隔离。

公开(公告)号：US20120083084A1

公开(公告)日：2012-04-05

申请号：US13199795

申请日：2011-09-08

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/1082

摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

摘要翻译： 沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。 围绕沟槽栅极的源极区域包括低势垒高度的金属，用作肖特基源，并且可以包括PtSi，ErSi层，并且可以是具有低势垒高度的金属硅化物层。 顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。 源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。

公开(公告)号：US20120028427A1

公开(公告)日：2012-02-02

申请号：US13200882

申请日：2011-10-04

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。