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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08546912B2

    公开(公告)日：2013-10-01

    申请号：US13440157

    申请日：2012-04-05

    申请人： Shunpei Yamazaki ,  Tatsuya Arao

    发明人： Shunpei Yamazaki ,  Tatsuya Arao

    IPC分类号： H01L21/08

    CPC分类号： H01L27/1266 ,  G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/13 ,  H01Q1/2208 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q23/00

    摘要： A semiconductor device such as an ID chip of the present invention includes an integrated circuit using a semiconductor element formed by using a thin semiconductor film, and an antenna connected to the integrated circuit. It is preferable that the antenna is formed integrally with the integrated circuit, since the mechanical strength of an ID chip can be enhanced. Note that the antenna used in the present invention also includes a conducting wire that is wound round circularly or spirally and fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are included is arranged between the conducting wires.

    摘要翻译： 本发明的ID芯片等半导体装置包括使用由半导体薄膜形成的半导体元件的集成电路和与集成电路连接的天线。 优选地，天线与集成电路一体形成，因为可以提高ID芯片的机械强度。 注意，本发明中使用的天线还包括绕圆形或螺旋状地缠绕的导线，并且在导线之间布置有软磁性材料的细小颗粒。 具体而言，在导线之间配置有软磁性材料的细微粒子的绝缘层。 具体而言，在导线之间配置有包含软磁性材料的微粒的绝缘层。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08159043B2

    公开(公告)日：2012-04-17

    申请号：US10583365

    申请日：2005-03-09

    申请人： Shunpei Yamazaki ,  Tatsuya Arao

    发明人： Shunpei Yamazaki ,  Tatsuya Arao

    IPC分类号： H01L21/08

    CPC分类号： H01L27/1266 ,  G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/13 ,  H01Q1/2208 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q23/00

    摘要： A semiconductor device such as an ID chip of the present invention includes an integrated circuit using a semiconductor element formed by using a thin semiconductor film, and an antenna connected to the integrated circuit. It is preferable that the antenna is formed integrally with the integrated circuit, since the mechanical strength of an ID chip can be enhanced. Note that the antenna used in the present invention also includes a conducting wire that is wound round circularly or spirally and fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are included is arranged between the conducting wires.

    摘要翻译： 本发明的ID芯片等半导体装置包括使用由半导体薄膜形成的半导体元件的集成电路和与集成电路连接的天线。 优选地，天线与集成电路一体形成，因为可以提高ID芯片的机械强度。 注意，本发明中使用的天线还包括绕圆形或螺旋状地缠绕的导线，并且在导线之间布置有软磁性材料的细小颗粒。 具体而言，在导线之间配置有软磁性材料的细微粒子的绝缘层。 具体而言，在导线之间配置有包含软磁性材料的微粒的绝缘层。

    Electro-optically active organic diode with short protection
    3.
    发明授权
    Electro-optically active organic diode with short protection 有权
    电光保护有机二极管

    公开(公告)号：US07985966B2

    公开(公告)日：2011-07-26

    申请号：US12373766

    申请日：2007-07-12

    申请人： Michael Buechel ,  Edward Willem Albert Young

    发明人： Michael Buechel ,  Edward Willem Albert Young

    IPC分类号： H01L21/08

    CPC分类号： H01L51/50 ,  H01L51/5092 ,  H01L51/5096 ,  H01L51/5221 ,  H01L51/5253 ,  H01L2251/5361 ,  H01L2251/5392

    摘要： An electro-optically active organic diode, for example an organic light emitting diode (OLED), comprises an anode electrode (102), a cathode electrode (122) and an electro-optically active organic layer (110) arranged in-between. A cover layer (124) is arranged in contact with a surface of the cathode layer (122) so that the cathode layer (122) is positioned between the organic layer (110) and the cover layer (124), which is formed of a substantially inert material with respect to a cathode layer (122) material in contact with said cover layer (124). The inert material is deposited on said surface of the cathode layer (122) so that the complete surface is covered and surface defects eliminated. A short protection layer (120) is further arranged between said cathode electrode (122) and said electro-optically active organic layer (110), and adjacent to said cathode electrode (122), and is formed of an inorganic semiconductor material. The cover layer (124) and the short protection layer (120) together reduce the risk of shorts to occur between the cathode (122) and the anode (102) and thus increase reliability of the electro-optically active organic diode.

    摘要翻译： 电光活性有机二极管，例如有机发光二极管（OLED），包括阳极电极（102），阴极电极（122）和布置在其间的电光活性有机层（110）。 覆盖层（124）被布置成与阴极层（122）的表面接触，使得阴极层（122）位于有机层（110）和覆盖层（124）之间，该层由 基本上惰性的材料相对于与所述覆盖层（124）接触的阴极层（122）材料。 惰性材料沉积在阴极层（122）的所述表面上，使得完整的表面被覆盖并且消除了表面缺陷。 在所述阴极电极（122）和所述电光活性有机层（110）之间，并且与所述阴极电极（122）相邻，并且由无机半导体材料形成的短保护层（120）。 覆盖层（124）和短保护层（120）一起降低阴极（122）和阳极（102）之间发生短路的风险，从而提高电光活性有机二极管的可靠性。

    Thin film bulk acoustic wave sensor suite
    4.
    发明授权
    Thin film bulk acoustic wave sensor suite 失效
    薄膜体声波传感器套件

    公开(公告)号：US07193352B1

    公开(公告)日：2007-03-20

    申请号：US11081894

    申请日：2005-03-11

    申请人： Arthur Ballato ,  Richard H. Wittstruck ,  Xiaojun Tong ,  Yicheng Lu

    发明人： Arthur Ballato ,  Richard H. Wittstruck ,  Xiaojun Tong ,  Yicheng Lu

    IPC分类号： H01L21/08 ,  H03H9/12

    CPC分类号： G01N29/022 ,  G01N2291/0256 ,  G01N2291/0423 ,  G01N2291/0426 ,  G01N2291/0427

    摘要： Thin film bulk acoustic wave sensors with coatings of biological and chemical materials, multiple electrode depositions and a piezo-active thin film transducer layer are hosted on a substrate. The thin film bulk acoustic wave sensor suite, or T-BASS, produces a low-voltage, IC-compliant thickness-directed electric field that is substantially uniform over a substantial portion of the active area of the BAW structure. The BAWs produced are essentially extensional plane waves propagating away from the substrate surface and having phase progression substantially oblique to the substrate surface. For BAW applications requiring sensing by an active layer, it would be most desirable to have an electrode structure that is both IC-compliant and can be energized from a low-voltage source of electrical energy. The thin film BAW sensors are compatible with IC fabrication and processing techniques, such as photolithography. Both single channel and multiple channel thin film bulk acoustic wave sensors are provided.

    摘要翻译： 具有生物和化学材料涂层，多电极沉积和压电有源薄膜换能器层的薄膜体声波传感器承载在基底上。 薄膜体声波传感器套件或T-BASS产生在BAW结构的有效区域的大部分上基本均匀的低电压，IC兼容的厚度导向电场。 所产生的BAW基本上是延伸的平面波，从衬底表面传播并具有基本上相对于衬底表面倾斜的相位进展。 对于需要通过有源层进行感测的BAW应用，最希望的是具有兼容IC的电极结构，并且可以从低电压电源通电。 薄膜BAW传感器与IC制造和处理技术（如光刻）兼容。 提供单通道和多通道薄膜体声波传感器。

    Method for forming residue free patterned polysilicon layers upon high step height integrated circuit substrates
    5.
    发明授权
    Method for forming residue free patterned polysilicon layers upon high step height integrated circuit substrates 失效
    在高阶高度集成电路基板上形成无残留图案化多晶硅层的方法

    公开(公告)号：US5792708A

    公开(公告)日：1998-08-11

    申请号：US611585

    申请日：1996-03-06

    申请人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

    发明人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

    IPC分类号： H01L21/3213 ,  H01L21/08

    CPC分类号： H01L21/32137

    摘要： A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer. The anisotropic first etch process is a Reactive Ion Etch (RIE) anisotropic first etch process which simultaneously passivates the exposed sidewall edges of the patterned polysilicon layer. Finally, the polysilicon residues formed at the lower step level of the high step height patterned substrate layer are removed through an isotropic second etch process. The isotropic second etch process is a Reactive Ion Etch (RIE) isotropic second etch process which employs hydrogen bromide (HBr) and sulfur hexafluoride (SF6) as the reactant gases.

    摘要翻译： 一种用于在高台阶高度图案化衬底层上形成无残留图案化多晶硅层的方法。 首先，提供在其上形成有高台阶高度图案化基板层的半导体基板。 形成在高台阶高度图案化衬底层上的是多晶硅层，并且在多晶硅层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层在高阶高度图案化衬底层的较低台阶处暴露多晶硅层的部分。 然后通过图案化的光致抗蚀剂层将多晶硅层图案化为使用各向异性第一蚀刻工艺的蚀刻掩模，以在高阶高度图案化衬底层的表面上产生图案化多晶硅层，并在高级步骤的较低级别处产生多晶硅残余物 高度图案化衬底层。 各向异性第一蚀刻工艺是反应离子蚀刻（RIE）各向异性第一蚀刻工艺，其同时钝化图案化多晶硅层的暴露的侧壁边缘。 最后，通过各向同性的第二蚀刻工艺去除在高阶高度图案化衬底层的较低台阶处形成的多晶硅残余物。 各向同性第二蚀刻工艺是使用溴化氢（HBr）和六氟化硫（SF6）作为反应气体的反应离子蚀刻（RIE）各向同性第二蚀刻工艺。

    Method of making a planar polysilicon bipolar device
    6.
    发明授权
    Method of making a planar polysilicon bipolar device 失效
    制造平面多晶硅双极器件的方法

    公开(公告)号：US4686763A

    公开(公告)日：1987-08-18

    申请号：US782838

    申请日：1985-10-02

    申请人： Mammen Thomas ,  Matthew Weinberg

    发明人： Mammen Thomas ,  Matthew Weinberg

    IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/08 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L29/66272 ,  H01L21/28525

    摘要： A highly planarized integrated circuit structure having at least one bipolar device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with openings defined therein respectively for formation of a collector contact region and a base/emitter region for a bipolar device in the substrate. All of the contacts of the bipolar device are formed using polysilicon which fills the defined openings in the field oxide resulting in a highly planarized structure.

    摘要翻译： 描述了具有至少一个双极器件的高度平坦化的集成电路结构以及制造该结构的方法。 该结构包括其上生长有其上限定有开口的场氧化物的衬底，用于形成集电极接触区域和用于衬底中的双极器件的基极/发射极区域。 双极器件的所有触点都是使用填充场氧化物中限定的开口的多晶硅形成的，形成高度平坦化的结构。