公开(公告)号：US20110007065A1

公开(公告)日：2011-01-13

申请号：US12923403

申请日：2010-09-20

申请人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

发明人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G5/001 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/061 ,  G09G2310/08

摘要： There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

公开(公告)号：US06995757B2

公开(公告)日：2006-02-07

申请号：US10460154

申请日：2003-06-13

申请人： Haruhisa Okumura ,  Yukihide Ode

发明人： Haruhisa Okumura ,  Yukihide Ode

IPC分类号： G09G5/00

CPC分类号： H03K19/00384 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/018571

摘要： A level converter circuit includes an input terminal adapted to be supplied with a signal swinging from a first voltage to a second voltage lower than the first voltage; a first transistor having a gate electrode connected to the input terminal, and a source electrode connected to ground potential; a second transistor having a gate electrode connected to a drain electrode of the first transistor, a source electrode connected to a supply voltage, and a drain electrode connected to an output terminal; a load circuit connected between the gate electrode of the second transistor and the supply voltage; a third transistor having a source electrode connected to the input terminal, a drain electrode connected to the output terminal, and a gate electrode supplied with a DC voltage higher than the second voltage and lower than the first voltage. The level converter circuit outputs a third voltage higher than the second voltage when the input terminal is supplied with the first voltage, and the level converter circuit outputs the second voltage when the input terminal is supplied with the second voltage.

公开(公告)号：US06924782B1

公开(公告)日：2005-08-02

申请号：US09182435

申请日：1998-10-30

申请人： Takahiro Fujioka ,  Kazunari Kurokawa ,  Hiroshi Katayanagi ,  Mitsuru Goto ,  Yukihide Ode ,  Akira Ogura ,  Kentaro Agata

发明人： Takahiro Fujioka ,  Kazunari Kurokawa ,  Hiroshi Katayanagi ,  Mitsuru Goto ,  Yukihide Ode ,  Akira Ogura ,  Kentaro Agata

IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1368 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/027

摘要： A liquid crystal display device has a semiconductor integrated circuit capable of outputting a voltage equal to or higher than the source-drain withstand voltage of a component transistor. A switching circuit has first conducting-type first and second transistors connected in series between a first input terminal and a common output terminal and second conducting-type third and fourth transistors connected between a second input terminal and the common output terminal and a switching control circuit for controlling the switching circuit. The switching control circuit applies first and second bias voltages for turning on the second and fourth transistors to the gate electrodes of the second and fourth transistors, and applies a control voltage for selectively turning on/off the first or third transistor to the gate electrodes of the first and third transistors.

摘要翻译： 液晶显示装置具有能够输出等于或高于分量晶体管的源极 - 漏极耐受电压的电压的半导体集成电路。 开关电路具有串联连接在第一输入端子和公共输出端子之间的第一导通型第一和第二晶体管，以及连接在第二输入端子和公共输出端子之间的第二导电型第三和第四晶体管，以及开关控制电路 用于控制开关电路。 开关控制电路施加用于将第二和第四晶体管导通到第二和第四晶体管的栅极的第一和第二偏置电压，并施加用于选择性地将第一或第三晶体管导通/截止到栅电极的控制电压 第一和第三晶体管。

公开(公告)号：US06731263B2

公开(公告)日：2004-05-04

申请号：US10143796

申请日：2002-05-14

申请人： Mitsuru Goto ,  Hiroshi Katayanagi ,  Yukihide Ode ,  Yoshiyuki Saitou ,  Koichi Kotera

发明人： Mitsuru Goto ,  Hiroshi Katayanagi ,  Yukihide Ode ,  Yoshiyuki Saitou ,  Koichi Kotera

IPC分类号： G09G336

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0289

摘要： Each video signal driver circuit in a liquid crystal display device includes a first amplifier circuit with a first output terminal and first and second input terminals; a second amplifier circuit with a second output terminal and third and fourth input terminals; a first connecting circuit switchable between a first connection wherein an output voltage from the first output terminal is input to the first input terminal as a reference voltage, and a second connection wherein the output voltage from the first output terminal is input to the second input terminal as a reference voltage; and a second connecting circuit switchable between a third connection wherein an output voltage from the second output terminal is input to the third input terminal as a reference voltage, and a fourth connection wherein the output voltage from the second output terminal is input to the fourth input terminal as a reference voltage.

摘要翻译： 液晶显示装置中的每个视频信号驱动电路包括具有第一输出端和第一和第二输入端的第一放大电路; 具有第二输出端子和第三和第四输入端子的第二放大器电路; 第一连接电路，其可以在第一连接之间切换，其中来自第一输出端子的输出电压被输入到第一输入端子作为参考电压;以及第二连接，其中来自第一输出端子的输出电压被输入到第二输入端子 作为参考电压; 以及第二连接电路，其可在第三连接之间切换，其中来自第二输出端子的输出电压作为参考电压输入到第三输入端子;以及第四连接，其中来自第二输出端子的输出电压被输入到第四输入端 端子作为参考电压。

公开(公告)号：US08416178B2

公开(公告)日：2013-04-09

申请号：US13200389

申请日：2011-09-23

申请人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

发明人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G5/001 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/061 ,  G09G2310/08

摘要： There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

摘要翻译： 需要减少在液晶显示装置中沿着栅极线的延伸方向的像素的TFT元件的写入时间的变化。 显示装置包括具有排列成矩阵的多个栅极线和漏极线的显示面板和用于向每条漏极线输出显示数据信号的数据驱动器。 数据驱动器包括：内部控制信号生成电路，其通过将多个排出线分割成多个块而产生内部控制信号，该内部控制信号用于设置通过块来将数据信号输出到每个块的漏极线的定时; 以及用于记录块的分割设置的寄存器电路，用于输出数据信号的定时的延迟方向和宽度的设置以及内部控制信号的上升和下降的设置。

公开(公告)号：US20130033658A1

公开(公告)日：2013-02-07

申请号：US13565233

申请日：2012-08-02

申请人： Takashi KATO ,  Yukihide ODE ,  Shunichi MATSUMOTO ,  Masato YANAI ,  Shimon ITAKURA ,  Tomohiro MAEYAMA

发明人： Takashi KATO ,  Yukihide ODE ,  Shunichi MATSUMOTO ,  Masato YANAI ,  Shimon ITAKURA ,  Tomohiro MAEYAMA

IPC分类号： G02F1/1333

CPC分类号： G02F1/13452 ,  G02F2001/133314 ,  G02F2201/465

摘要： In a liquid crystal display device in which a source board (56) connected to a liquid crystal panel by a flex circuit is mounted onto a rear surface of a lower metal frame (54), disconnection in the flex circuit or at a connection portion thereof is avoided. The source board (56) includes a conductor pattern (110) serving as a ground electrode held in contact with the rear surface of the frame (54). A support member (60) for supporting the circuit board (56) is fixed to the frame (54) and includes a cantilever (62) which extends above the source board (56), for pressing the source board (56) against the frame (54). The cantilever (62) enables displacement of the source board (56) along the rear surface of the frame (54) while maintaining a state in which the conductor pattern (110) is held in contact with the frame (54).

摘要翻译： 在液晶显示装置中，其中通过柔性电路连接到液晶面板的源极板（56）安装在下部金属框架（54）的后表面上，在柔性电路中或其连接部分处的断开 被避免。 源板（56）包括用作与框架（54）的后表面接触的接地电极的导体图案（110）。 用于支撑电路板（56）的支撑构件（60）固定到框架（54）上并包括在源板（56）上方延伸的悬臂（62），用于将源板（56）压靠在框架 （54）。 悬臂（62）使得源板（56）沿着框架（54）的后表面位移，同时保持导体图案（110）保持与框架（54）接触的状态。

公开(公告)号：US08159486B2

公开(公告)日：2012-04-17

申请号：US12216093

申请日：2008-06-30

申请人： Haruhisa Okumura ,  Yukihide Ode

发明人： Haruhisa Okumura ,  Yukihide Ode

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： H03K19/00384 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/018571

摘要： A display device includes a pixel driver circuit. Each of level converter circuits in the pixel driver circuit has an input terminal supplied with a signal swinging between a first voltage and a second voltage lower than the first voltage; a first first-conductivity-type transistor having a gate electrode coupled to the input terminal, and a source region coupled to a reference voltage; a second second-conductivity-type transistor having a gate electrode coupled to a drain region of the first transistor, a source region-coupled to a power supply, and a drain region coupled to an output terminal; one circuit element among a diode, a resistor and a fourth second-conductivity-type transistor, coupled between the gate electrode of the second transistor and the power supply; a third first-conductivity-type transistor having a source region coupled to the input terminal, a drain region coupled to the output terminal, and a gate electrode supplied with a do voltage.

摘要翻译： 显示装置包括像素驱动电路。 像素驱动电路中的每个电平转换器电路的输入端被提供有在第一电压和低于第一电压的第二电压之间摆动的信号; 第一第一导电型晶体管，其具有耦合到输入端子的栅极电极和耦合到参考电压的源极区域; 第二第二导电型晶体管，其具有耦合到所述第一晶体管的漏极区的栅极电极，耦合到电源的源极区域和耦合到输出端子的漏极区域; 耦合在第二晶体管的栅电极和电源之间的二极管，电阻器和第四第二导电型晶体管中的一个电路元件; 具有耦合到输入端子的源极区域的第三第一导电型晶体管，耦合到输出端子的漏极区域和提供有电压的栅极电极。

公开(公告)号：US08159437B2

公开(公告)日：2012-04-17

申请号：US13176993

申请日：2011-07-06

申请人： Mitsuru Goto ,  Hiroshi Katayanagi ,  Yukihide Ode ,  Yoshiyuki Saitou ,  Koichi Kotera

发明人： Mitsuru Goto ,  Hiroshi Katayanagi ,  Yukihide Ode ,  Yoshiyuki Saitou ,  Koichi Kotera

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0289

摘要： A semiconductor integrated circuit includes a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor, and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two frame periods.

摘要翻译： 半导体集成电路包括锁存显示数据的第一寄存器，根据第一时钟锁存第一寄存器的显示数据的第二寄存器，输出多个灰度级电压的灰度级电压发生器，选择 根据来自多个灰度级电压的第二寄存器的显示数据的灰度级电压，以及包括第一晶体管和第二晶体管的放大器。 第一晶体管的第一端子和第二晶体管的第一端子连接到第一电压线，并且从解码器输出的灰度电压根据第一晶体管的第一端子被提供给第一晶体管和第二晶体管的输入端 一个控制信号。 控制信号的相位以两帧周期的间隔反转。

公开(公告)号：US07408544B2

公开(公告)日：2008-08-05

申请号：US11283745

申请日：2005-11-22

申请人： Haruhisa Okumura ,  Yukihide Ode

发明人： Haruhisa Okumura ,  Yukihide Ode

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： H03K19/00384 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/018571

摘要： A display device includes a pixel driver circuit. Each of level converter circuits in the pixel driver circuit has: an input terminal supplied with a signal swinging between a first voltage and a second voltage lower than the first voltage; a first first-conductivity-type transistor having a gate electrode coupled to the input terminal, and a source region coupled to ground; a second second-conductivity-type transistor having a gate electrode coupled to a drain region of the first transistor, a source region coupled to a power supply, and a drain region coupled to an output terminal; one circuit element among a diode, a resistor and a fourth second-conductivity-type transistor, coupled between the gate electrode of the second transistor and the power supply; a third first-conductivity-type transistor having a source region coupled to the input terminal, a drain region coupled to the output terminal, and a gate electrode supplied with a dc voltage.

摘要翻译： 显示装置包括像素驱动电路。 像素驱动电路中的每个电平转换器电路具有：提供在第一电压和低于第一电压的第二电压之间摆动的信号的输入端; 具有耦合到输入端的栅极的第一第一导电型晶体管和耦合到地的源极区; 第二第二导电型晶体管，其具有耦合到第一晶体管的漏极区的栅极电极，耦合到电源的源极区域和耦合到输出端子的漏极区域; 耦合在第二晶体管的栅电极和电源之间的二极管，电阻器和第四第二导电型晶体管中的一个电路元件; 具有耦合到输入端子的源极区域的第三第一导电型晶体管，耦合到输出端子的漏极区域和被提供有直流电压的栅极电极。

公开(公告)号：US20070152947A1

公开(公告)日：2007-07-05

申请号：US11639149

申请日：2006-12-15

申请人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

发明人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

IPC分类号： G09G3/36

CPC分类号： G09G5/001 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/061 ,  G09G2310/08

摘要： There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting foradelay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

摘要翻译： 需要减少在液晶显示装置中沿着栅极线的延伸方向的像素的TFT元件的写入时间的变化。 显示装置包括具有多个栅极线和排列成矩阵的多个漏极线的显示面板和用于向每条漏极线输出显示数据信号的数据驱动器。 数据驱动器包括：内部控制信号发生电路，用于通过将多个排出线分成多个块来产生用于设置定时的内部控制信号，以将数据信号以块的形式输出到每个块的漏极线; 以及用于记录块的分割设置的寄存器电路，用于输出数据信号的定时的设置方向和延迟宽度以及内部控制信号的上升和下降的设置。