公开(公告)号：US20080285251A1

公开(公告)日：2008-11-20

申请号：US11910893

申请日：2006-04-06

申请人： Jerry Liang ,  Jieren Xie ,  Xinchao Wang ,  Xiekang Yu ,  Yujuan Tao ,  Rongfu Wen ,  Fushou Li ,  Zhengwei Zhou ,  Da Wang ,  Haibo Ge ,  Qiang Zheng ,  Zhen Gong ,  Weijun Yang

发明人： Jerry Liang ,  Jieren Xie ,  Xinchao Wang ,  Xiekang Yu ,  Yujuan Tao ,  Rongfu Wen ,  Fushou Li ,  Zhengwei Zhou ,  Da Wang ,  Haibo Ge ,  Qiang Zheng ,  Zhen Gong ,  Weijun Yang

IPC分类号： H05K7/18 ,  H01R43/00

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49121 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A packaging substrate with fiat bumps for an electronic device and a method of manufacturing the same relate to the production of the packaging substrate for an electronic device, which comprises base islands and pins structurally and wherein the base islands and pins which all exhibit flat bump shape distribute on the front face of the substrate; the bottom side of the bumps, namely the rear faces of the base islands and pins are contiguous in the same substrate; in the packaging body of a single electronic device to be formed in later procedure, one or more base island may be included, the pins may arrange on one single side of the base island, also may arrange on the both sides or three sides of the base island, or may surround the base island so as to form the structure of one or more circuits of pins. The method includes that take a metal substrate is prepared, mask layers are adhered onto both sides of the metal substrate, the parts of the mask layers which need to be etched are removed, then half-etching is performed to form the recessed half-etching area, and then the residual mask layers on the metal substrate are removed to product the packaging substrate with flat bumps.

摘要翻译： 一种用于电子器件的具有凸点的封装衬底及其制造方法涉及用于电子器件的封装衬底的生产，该电子器件的结构包括基极岛和引线，并且其中所有基体岛和引脚均呈现平坦的凸起形状 分布在基板的正面上; 凸起的底面，即基部岛和针的后表面在相同的基底中是连续的; 在稍后的步骤中形成的单个电子设备的包装体中，可以包括一个或多个基岛，该引脚可以布置在基岛的单个侧面上，也可以布置在基底岛的两侧或三侧上 或者可以围绕基岛，以形成一个或多个引脚电路的结构。 该方法包括：制备金属基板，将掩模层粘附到金属基板的两侧，去除需要蚀刻的掩模层的部分，然后进行半蚀刻以形成凹入的半蚀刻 区域，然后去除金属基板上的残留掩模层，以产生具有扁平凸块的封装基板。

公开(公告)号：US20080315412A1

公开(公告)日：2008-12-25

申请号：US11910885

申请日：2006-04-06

申请人： Jerry Liang ,  Jieren Xie ,  Xinchao Wang ,  Xiekang Yu ,  Yujuan Tao ,  Rongfu Wen ,  Fushou Li ,  Zhengwei Zhou ,  Da Wang ,  Haibo Ge ,  Qiang Zheng ,  Zhen Gong ,  Weijun Yang

发明人： Jerry Liang ,  Jieren Xie ,  Xinchao Wang ,  Xiekang Yu ,  Yujuan Tao ,  Rongfu Wen ,  Fushou Li ,  Zhengwei Zhou ,  Da Wang ,  Haibo Ge ,  Qiang Zheng ,  Zhen Gong ,  Weijun Yang

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49121 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： The invention discloses a novel package structure of integrate circuit or discrete device and packaging method, and includes the lead pins adjacent to the island; another metal layer formed at the bottom of the island; another metal layer formed at the bottom of lead pins; chip mounted on the island; wires bonded between the chip and the lead pins; the molded body encapsulating the top surface and side surface of the island and the lead pins, small protrusions of the island and the lead pins below the molded body; in the individual package, the number of the island can be one or more, lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. The invention provides strong welding, good quality, low cost, smooth production, wide applicability, flexible arrangement of the chips.

摘要翻译： 本发明公开了一种集成电路或分立器件和封装方法的新型封装结构，其中包括与岛相邻的引脚; 在岛底形成另一金属层; 在引脚的底部形成另一金属层; 芯片安装在岛上; 引线接合在芯片和引脚之间; 封装岛状物的顶面和侧面以及引线销的成型体，岛状体的小突起和成形体下方的引线销; 在单个封装中，岛的数量可以是一个或多个，引脚可以排列在岛的一侧，也可以排列在岛的两侧或三侧，一行或两排引脚可以 位于岛周围。 本发明提供焊接牢固，质量好，成本低，生产流畅，适用范围广，芯片布置灵活。

公开(公告)号：US20080258273A1

公开(公告)日：2008-10-23

申请号：US11910878

申请日：2006-04-06

申请人： Jerry Liang ,  Jieren Xie ,  Xinchao Wang ,  Xiekang Yu ,  Yujuan Tao ,  Rongfu Wen ,  Fushou Li ,  Zhengwei Zhou ,  Da Wang ,  Haibo Ge ,  Qiang Zheng ,  Zhen Gong ,  Weijun Yang

发明人： Jerry Liang ,  Jieren Xie ,  Xinchao Wang ,  Xiekang Yu ,  Yujuan Tao ,  Rongfu Wen ,  Fushou Li ,  Zhengwei Zhou ,  Da Wang ,  Haibo Ge ,  Qiang Zheng ,  Zhen Gong ,  Weijun Yang

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49121 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and side surface of the chip support base, small protrusions of the chip support base and lead support base below the molded body; in the individual package, the number of the chip support base island can be one or more, the lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island.

摘要翻译： 本发明公开了一种无铅电子器件的超薄封装结构及其封装方法，包括与芯片支撑基座相邻的引线支撑基座; 芯片安装在芯片支撑基座上; 芯片和引线支撑基座之间接合的导线; 包封芯片支撑基座的上表面和侧表面的成型体，芯片支撑基座的小突起和模制体下方的引线支撑基座; 在单个封装中，芯片支撑基岛的数量可以是一个或多个，引脚可以排列在岛的一侧，也可以排列在岛的两侧或三侧，一行或两行 的引脚可以位于岛周围。