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公开(公告)号：US20210099278A1
公开(公告)日：2021-04-01
申请号：US16584012
申请日：2019-09-26
Applicant: Apple Inc.
Inventor： Michael F. Jean , Adam E. Kriegel , Brett D. George , Daniel C. Klingler , Girault W. Jones , Felipe Ferreri Tonello
Abstract: A system and method to mitigate the temporary loss of the input sampling clocks when receiving audio data over the ARC or eARC interface of HDMI are provided. A media device may substitute an externally generated clock derived from a local crystal oscillator of the media device for the missing input sampling clock. The external clock may be synchronized to the frequency of the input sampling clock. The media device may synchronize the external clock to the audio data when there is a loss of the input sampling clock. When the input sampling clock of the audio data reappears, the media device may switch back from the external clock to the input sampling clock. When transitioning between the input sampling clock and the external clock, the media device may insert zero padding into the audio data samples to mute any potential glitch in the sound from an audio playback device.
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公开(公告)号：US09928838B2
公开(公告)日：2018-03-27
申请号：US15482142
申请日：2017-04-07
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
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公开(公告)号：US20170213557A1
公开(公告)日：2017-07-27
申请号：US15482142
申请日：2017-04-07
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
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公开(公告)号：US20150382104A1
公开(公告)日：2015-12-31
申请号：US14315863
申请日：2014-06-26
Applicant: Apple Inc.
Inventor： Roderick B. Hogan , Girault W. Jones , Nathan A. Johanningsmeier
IPC: H04R3/00
CPC classification number: H04R3/00 , H04R2420/09 , H04R2499/13
Abstract: A method for audio signal processing, where an audio amplifier drives a load through a connector, using 1) an input audio signal, and 2) a signal from a return pin of the connector. Output headroom of the audio amplifier is automatically detected, while the amplifier is driving the load. A variable resistor circuit that is coupled to provide variable resistance between the return pin of the connector and a ground plane, is automatically adjusted, in response to the detected output headroom of the amplifier. Other embodiments are also described and claimed.
Abstract translation: 一种用于音频信号处理的方法，其中音频放大器通过连接器驱动负载，使用1）输入音频信号，以及2）来自所述连接器的返回引脚的信号。 当放大器驱动负载时，自动检测音频放大器的输出净空。 响应于检测到的放大器的输出净空，自动调整耦合以提供连接器的返回引脚和接地平面之间的可变电阻的可变电阻器电路。 还描述和要求保护其他实施例。
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公开(公告)号：US20140207983A1
公开(公告)日：2014-07-24
申请号：US13747205
申请日：2013-01-22
Applicant: APPLE INC.
Inventor： Girault W. Jones , Nathan A. Johanningsmeier , Casey L. Hardy
IPC: G06F13/38
CPC classification number: G06F13/4291 , Y02D10/14 , Y02D10/151
Abstract: An audio system bus has a bus data line and a bus clock line. Audio producers are coupled to the bus to form a time-division multiplexed multi drop bus interface arrangement having protocol slots 0,1, . . . N where N is an integer greater than two. A bus device is coupled to the bus that produces a) a frame marker on the bus data line in slot 0, and b) a data bit on the bus data line in slot 1. The audio producers are to produce their respective audio data bits in their assigned slots other than slots 0 and 1. Other embodiments are also described and claimed.
Abstract translation: 音频系统总线具有总线数据线和总线时钟线。 音频产生器耦合到总线以形成具有协议时隙0,1的时分复用多载波总线接口装置。 。 。 N，其中N是大于2的整数。 总线设备耦合到总线，该总线产生a）在时隙0中的总线数据线上的帧标记，以及b）时隙1中总线数据线上的数据位。音频制作者将产生它们各自的音频数据位 在它们分配的时隙中，除了时隙0和1之外，还描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US20210098011A1
公开(公告)日：2021-04-01
申请号：US16584008
申请日：2019-09-26
Applicant: Apple Inc.
Inventor： Brett D. George , Adam E. Kriegel , Michael F. Jean , Daniel C. Klingler , Girault W. Jones , Felipe Ferreri Tonello
IPC: G10L19/16
Abstract: A system and method to process audio data received over the ARC or eARC interface of HDMI from audio sources are provided. A media device may receive compressed audio data in a number of data formats. The media device may convert between the audio formats provided by the audio sources and the audio formats supported by audio playback devices. The media device may inspect frames of audio data to determine if the frames are to be decoded. The frame may be decoded and subsequently encoded into the data formats supported by the audio playback devices. To reduce latency, the media device may enable a pass-through mode to bypass the decoding of the frames to allow the frames to be decoded at the audio playback devices. A bi-directional loopback application may route audio data received over the ARC or eARC interface from the audio sources to the audio playback devices.
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公开(公告)号：US09699558B2
公开(公告)日：2017-07-04
申请号：US13712327
申请日：2012-12-12
Applicant: Apple Inc.
Inventor： Girault W. Jones , Nathan A. Johanningsmeier , Martin E. Johnson
Abstract: A multi-channel audio system that can provide a variable sub-sample delay between two or more audio channels. In one embodiment, a variable timing clock generator generates multiple clock signals where each may have different phase, and the clock generator can vary the phase difference, in accordance with a sub-sample delay setting input. These clock signals are used by respective digital-to-analog converters (DACs) to convert the digital audio channels into analog form. In another embodiment, a variable delay block is added to an oversampling DAC, on a per channel basis. Other embodiments are also described and claimed.
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公开(公告)号：US20140161279A1
公开(公告)日：2014-06-12
申请号：US13712327
申请日：2012-12-12
Applicant: APPLE INC.
Inventor： Girault W. Jones , Nathan A. Johanningsmeier , Martin E. Johnson
IPC: H04R3/12
Abstract: A multi-channel audio system that can provide a variable sub-sample delay between two or more audio channels. In one embodiment, a variable timing clock generator generates multiple clock signals where each may have different phase, and the clock generator can vary the phase difference, in accordance with a sub-sample delay setting input. These clock signals are used by respective digital-to-analog converters (DACs) to convert the digital audio channels into analog form. In another embodiment, a variable delay block is added to an oversampling DAC, on a per channel basis. Other embodiments are also described and claimed.
Abstract translation: 可以在两个或多个音频通道之间提供可变子采样延迟的多声道音频系统。 在一个实施例中，可变定时时钟发生器产生多个时钟信号，其中每个时钟信号可以具有不同的相位，并且时钟发生器可以根据子采样延迟设置输入来改变相位差。 这些时钟信号由相应的数模转换器（DAC）用于将数字音频通道转换为模拟形式。 在另一个实施例中，可变延迟块以每通道为基础被添加到过采样DAC。 还描述和要求保护其他实施例。
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公开(公告)号：US11514921B2
公开(公告)日：2022-11-29
申请号：US16584008
申请日：2019-09-26
Applicant: Apple Inc.
Inventor： Brett D. George , Adam E. Kriegel , Michael F. Jean , Daniel C. Klingler , Girault W. Jones , Felipe Ferreri Tonello
IPC: G10L19/16
Abstract: A system and method to process audio data received over the ARC or eARC interface of HDMI from audio sources are provided. A media device may receive compressed audio data in a number of data formats. The media device may convert between the audio formats provided by the audio sources and the audio formats supported by audio playback devices. The media device may inspect frames of audio data to determine if the frames are to be decoded. The frame may be decoded and subsequently encoded into the data formats supported by the audio playback devices. To reduce latency, the media device may enable a pass-through mode to bypass the decoding of the frames to allow the frames to be decoded at the audio playback devices. A bi-directional loopback application may route audio data received over the ARC or eARC interface from the audio sources to the audio playback devices.
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公开(公告)号：US20180350405A1
公开(公告)日：2018-12-06
申请号：US15610431
申请日：2017-05-31
Applicant: Apple Inc.
Inventor： Todd P. Marco , Girault W. Jones , Kavitha Srinivasan , Aram M. Lindahl
IPC: G11B27/031 , H04N5/77 , H04R3/00 , G06K9/00 , H04N5/92 , G11B27/19 , H04N5/262 , G10L25/57 , H04N5/265
Abstract: A method for automatically producing a video and audio mix at a first portable electronic device. The method receives a request to capture video and audio, performs a network discovery process to find a second portable electronic device, and sends a message to the second device indicating when to start recording audio for a double system recording session. The method initiates the recording session, such that both devices record concurrently. In response to the first device stopping the recording of audio and sound, signaling the second device to stop recording for the identified recording session. In response to the first device receiving a first audio track from the second device that contains an audio signal recorded during the recording session, automatically generating a mix of video and audio, such that one of the audio signals from the first and second tracks is ducked relative to the other.
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