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公开(公告)号：US20210341317A1
公开(公告)日：2021-11-04
申请号：US17372764
申请日：2021-07-12
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
IPC: G01D9/00 , G06F13/16 , G06F1/3293 , G06F1/3206 , G06F1/3287
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US10261894B2
公开(公告)日：2019-04-16
申请号：US15447328
申请日：2017-03-02
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
IPC: G06F12/02 , G06F12/06 , G06F1/32 , G06F3/06 , G06F9/44 , G06F13/16 , G06F13/40 , G11C11/406 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F9/4401 , G06F13/42
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US10048720B2
公开(公告)日：2018-08-14
申请号：US15831732
申请日：2017-12-05
Applicant: Apple Inc.
Inventor： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC: G06F1/12
Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.
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公开(公告)号：US10031000B2
公开(公告)日：2018-07-24
申请号：US14458885
申请日：2014-08-13
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G01D9/00 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/122 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US09959124B1
公开(公告)日：2018-05-01
申请号：US14498428
申请日：2014-09-26
Applicant: Apple Inc.
Inventor： Gilbert H. Herbeck , Manu Gulati , Erik P. Machnicki , Timothy R. Paaske
CPC classification number: G06F9/4401 , G06F1/3287 , G06F9/4411 , G06F9/4418
Abstract: In an embodiment, a system includes a functional unit that remains powered when the remainder of the system is powered off. The functional unit may, in response to a transition from a first power state to a second power state, retrieve configuration information from a read-only memory. In some embodiments, may be configured to store at least a portion of the configured information in a secure portion of a memory included in the functional unit and then lock the secure portion of the memory. The functional unit may then complete the transition to the second power state.
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Patent Agency Ranking
公开(公告)号：US09864399B2
公开(公告)日：2018-01-09
申请号：US14965073
申请日：2015-12-10
Applicant: Apple Inc.
Inventor： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC: G06F1/12
Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.
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7.发明授权公开(公告)号：US09395747B1
公开(公告)日：2016-07-19
申请号：US14592146
申请日：2015-01-08
Applicant: Apple Inc.
Inventor： Gilbert H. Herbeck , Gregoire J. Le Grand de Mercey
CPC classification number: G06F1/12
Abstract: Various embodiments of a clock generator are disclosed. An example system may include a functional unit, and a clock generation unit configured to adjust a frequency of an output clock signal responsive to an assertion of an enable signal from the functional unit. The clock generation unit may also be configured to halt the output clock signal responsive to a de-assertion of the enable signal by the functional unit and to restart the output clock signal responsive to a determination that a first predetermined amount of time has elapsed since the output clock signal was halted. The clock generation unit may be further configured to adjust the frequency of the output clock signal responsive to restarting the output clock signal, and to halt the output clock signal responsive to a determination that the frequency of the output clock signal is within a predetermined frequency range that includes the target frequency.
Abstract translation: 公开了时钟发生器的各种实施例。 示例性系统可以包括功能单元，以及时钟生成单元，被配置为响应于来自功能单元的使能信号的断言来调整输出时钟信号的频率。 时钟生成单元还可以被配置为响应于功能单元的使能信号的断言而停止输出时钟信号，并且响应于从第一预定时间量过去的确定重新启动输出时钟信号 输出时钟信号停止。 时钟生成单元还可以被配置为响应于重新启动输出时钟信号来调整输出时钟信号的频率，并响应于输出时钟信号的频率在预定频率范围内的确定而停止输出时钟信号 包括目标频率。
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8.发明授权公开(公告)号：US12117320B2
公开(公告)日：2024-10-15
申请号：US17366459
申请日：2021-07-02
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal , Michael F. Culbert
IPC: G01D9/00 , A61G3/06 , B60P1/43 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/16
CPC classification number: G01D9/00 , A61G3/061 , B60P1/433 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/00 , Y02D30/50
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.
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公开(公告)号：US20190260799A1
公开(公告)日：2019-08-22
申请号：US16276504
申请日：2019-02-14
Applicant: Apple Inc.
Inventor： Zhimin Chen , Timothy R. Paaske , Gilbert H. Herbeck
Abstract: A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.
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公开(公告)号：US20180313673A1
公开(公告)日：2018-11-01
申请号：US16019087
申请日：2018-06-26
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G01D9/00 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/122 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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